Search

Habte Mered

Examiner (ID: 220, Phone: (571)272-6046 , Office: P/2474 )

Most Active Art Unit
2474
Art Unit(s)
2474, 2662, 2416, 2616
Total Applications
972
Issued Applications
735
Pending Applications
69
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18661332 [patent_doc_number] => 20230307346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/160525 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160525
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Jan 26, 2023 Abandoned
Array ( [id] => 18848871 [patent_doc_number] => 20230411275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/096132 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096132 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096132
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME Jan 11, 2023 Pending
Array ( [id] => 19054880 [patent_doc_number] => 20240096849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR STRUCTURE, STACKED STRUCTURE, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/152141 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152141 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152141
Semiconductor structure, stacked structure with terminal comprising capping layer and manufacturing method thereof Jan 8, 2023 Issued
Array ( [id] => 18653223 [patent_doc_number] => 20230299063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SPHERICAL DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/089058 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089058
Spherical display device having through holes between pixel structures of a plurality of display units Dec 26, 2022 Issued
Array ( [id] => 19191472 [patent_doc_number] => 20240170385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/145198 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145198
Semiconductor package device having at least one second metal line between two adjacent first metal lines of redistribution layer Dec 21, 2022 Issued
Array ( [id] => 20612907 [patent_doc_number] => 12588528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Package bumps of a package substrate having diagonal package bumps [patent_app_type] => utility [patent_app_number] => 18/069044 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/069044
Package bumps of a package substrate having diagonal package bumps Dec 19, 2022 Issued
Array ( [id] => 20216214 [patent_doc_number] => 12412869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Electronic structure having first and second thermal conductive materials covering conductive bumps and manufacturing method thereof, and electronic package having electronic structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/063115 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 1104 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063115
Electronic structure having first and second thermal conductive materials covering conductive bumps and manufacturing method thereof, and electronic package having electronic structure and manufacturing method thereof Dec 7, 2022 Issued
Array ( [id] => 20484266 [patent_doc_number] => 12532747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Semiconductor package and package-on-package having different wiring insulating layers surrounding differential signal wiring layers [patent_app_type] => utility [patent_app_number] => 18/075878 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075878
Semiconductor package and package-on-package having different wiring insulating layers surrounding differential signal wiring layers Dec 5, 2022 Issued
Array ( [id] => 18516333 [patent_doc_number] => 20230232655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/061019 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061019 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061019
Display device with optical compensation layer of low refractive index and method of manufacturing the same Dec 1, 2022 Issued
Array ( [id] => 20540122 [patent_doc_number] => 12557209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Printed circuit board having cutting position identification mark and alignment mark and semiconductor package having the same [patent_app_type] => utility [patent_app_number] => 18/071903 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3381 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071903 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/071903
Printed circuit board having cutting position identification mark and alignment mark and semiconductor package having the same Nov 29, 2022 Issued
Array ( [id] => 20389366 [patent_doc_number] => 12489101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Electronic devices having inner electronic component interposed between substrates and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/994355 [patent_app_country] => US [patent_app_date] => 2022-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 33 [patent_no_of_words] => 6296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994355
Electronic devices having inner electronic component interposed between substrates and method of manufacturing the same Nov 26, 2022 Issued
Array ( [id] => 20346090 [patent_doc_number] => 12469825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Power semiconductor device and power semiconductor module each having electrodes on opposing surfaces of power semiconductor chip [patent_app_type] => utility [patent_app_number] => 17/991995 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 43 [patent_no_of_words] => 12644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991995
Power semiconductor device and power semiconductor module each having electrodes on opposing surfaces of power semiconductor chip Nov 21, 2022 Issued
Array ( [id] => 19029986 [patent_doc_number] => 11929352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Semiconductor memory device having transistors between bonding pads and word lines [patent_app_type] => utility [patent_app_number] => 17/984959 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 17299 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/984959
Semiconductor memory device having transistors between bonding pads and word lines Nov 9, 2022 Issued
Array ( [id] => 19016346 [patent_doc_number] => 11923288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Wiring substrate, electronic device, and electronic module each having plate-shaped conductive portion in frame portion of insulation substrate [patent_app_type] => utility [patent_app_number] => 17/977764 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6862 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/977764
Wiring substrate, electronic device, and electronic module each having plate-shaped conductive portion in frame portion of insulation substrate Oct 30, 2022 Issued
Array ( [id] => 19086248 [patent_doc_number] => 20240113049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => PACKAGE SUBSTRATE WITH OPEN AIR GAP STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/937474 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937474
PACKAGE SUBSTRATE WITH OPEN AIR GAP STRUCTURES Oct 2, 2022 Pending
Array ( [id] => 19086205 [patent_doc_number] => 20240113006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER [patent_app_type] => utility [patent_app_number] => 17/937519 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937519 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937519
PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER Oct 2, 2022 Pending
Array ( [id] => 19086169 [patent_doc_number] => 20240112970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES [patent_app_type] => utility [patent_app_number] => 17/957355 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957355
SINGULATION OF INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES Sep 29, 2022 Pending
Array ( [id] => 19086206 [patent_doc_number] => 20240113007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES [patent_app_type] => utility [patent_app_number] => 17/958012 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958012
AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES Sep 29, 2022 Pending
Array ( [id] => 18920646 [patent_doc_number] => 20240023650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => WORKWEAR UNIT HAVING A GLOVE THAT FASTENS A CONTROL SYSTEM AND FUNCTIONAL MODULE TO A USER'S BODY [patent_app_type] => utility [patent_app_number] => 17/952205 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952205
WORKWEAR UNIT HAVING A GLOVE THAT FASTENS A CONTROL SYSTEM AND FUNCTIONAL MODULE TO A USER'S BODY Sep 22, 2022 Pending
Array ( [id] => 18906022 [patent_doc_number] => 20240021507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => VIA CONNECTION STRUCTURE COMPRISING MULTIPLE VIAS AND SUBSTRATE COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 18/010254 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18010254 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/010254
VIA CONNECTION STRUCTURE COMPRISING MULTIPLE VIAS AND SUBSTRATE COMPRISING THE SAME Sep 8, 2022 Pending
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