Hafizur Rahman

Array ( [id] => 8455027 [patent_doc_number] => 20120265973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'High Reliability Processor System' [patent_app_type] => utility [patent_app_number] => 13/088597 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4692 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8536161 [patent_doc_number] => 08312326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Delta checkpoints for a non-volatile memory indirection table' [patent_app_type] => utility [patent_app_number] => 13/084890 [patent_app_country] => US [patent_app_date] => 2011-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2737 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13084890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7735875 [patent_doc_number] => 20120017116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 13/082048 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4811 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20120017116.pdf [firstpage_image] =>[orig_patent_app_number] => 13082048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5990815 [patent_doc_number] => 20110099450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof' [patent_app_type] => utility [patent_app_number] => 12/982918 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8998 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099450.pdf [firstpage_image] =>[orig_patent_app_number] => 12982918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9314998 [patent_doc_number] => 08656233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Scan cell designs with serial and parallel loading of test data' [patent_app_type] => utility [patent_app_number] => 12/982642 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4239 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9248510 [patent_doc_number] => 08612812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Semiconductor memory device, test circuit, and test operation method thereof' [patent_app_type] => utility [patent_app_number] => 12/982607 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5593 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9169882 [patent_doc_number] => 08595575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor memory device, test circuit, and test operation method thereof' [patent_app_type] => utility [patent_app_number] => 12/982423 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7610 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8222975 [patent_doc_number] => 20120137166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'STORAGE SYSTEM USING SAS STANDARD BACK-END COMMUNICATION' [patent_app_type] => utility [patent_app_number] => 13/000002 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 13679 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13000002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8971800 [patent_doc_number] => 08510629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Memory module on which regular chips and error correction chips are mounted' [patent_app_type] => utility [patent_app_number] => 12/908512 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 41 [patent_no_of_words] => 8885 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12908512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6040710 [patent_doc_number] => 20110093759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'TRANSMITTING SYSTEM AND METHOD OF PROCESSING DIGITAL BROADCAST SIGNAL IN TRANSMITTING SYSTEM, RECEIVING SYSTEM AND METHOD OF RECEIVING DIGITAL BROADCAST SIGNAL IN RECEIVING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/907649 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 87 [patent_figures_cnt] => 87 [patent_no_of_words] => 57286 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093759.pdf [firstpage_image] =>[orig_patent_app_number] => 12907649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9257878 [patent_doc_number] => 08621319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Method and apparatus for iterative determination of MIMO iterative receiver' [patent_app_type] => utility [patent_app_number] => 12/904665 [patent_app_country] => US [patent_app_date] => 2010-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4037 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12904665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8623300 [patent_doc_number] => 08356221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Transition delay test function logic' [patent_app_type] => utility [patent_app_number] => 12/861991 [patent_app_country] => US [patent_app_date] => 2010-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5543 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12861991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7785852 [patent_doc_number] => 20120047408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'SYSTEMS AND METHODS FOR MEMORY MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 12/860172 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10108 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20120047408.pdf [firstpage_image] =>[orig_patent_app_number] => 12860172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7588657 [patent_doc_number] => 20110283168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'Method of Handling Packet Loss Using Error-Correcting Codes and Block Rearrangement' [patent_app_type] => utility [patent_app_number] => 12/859794 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5746 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283168.pdf [firstpage_image] =>[orig_patent_app_number] => 12859794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8728417 [patent_doc_number] => 08407558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Code-assisted error-detection technique' [patent_app_type] => utility [patent_app_number] => 12/858923 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8853 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12858923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787121 [patent_doc_number] => 08433975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Bitwise reliability indicators from survivor bits in Viterbi decoders' [patent_app_type] => utility [patent_app_number] => 12/856143 [patent_app_country] => US [patent_app_date] => 2010-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12856143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6153867 [patent_doc_number] => 20110022888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'INFORMATION PROCESSING APPARATUS, CONTROL METHOD OF THE INFORMATION PROCESSING APPARATUS, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/837865 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5772 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022888.pdf [firstpage_image] =>[orig_patent_app_number] => 12837865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7582374 [patent_doc_number] => 20110296257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'POST CARD' [patent_app_type] => utility [patent_app_number] => 12/835706 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2448 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296257.pdf [firstpage_image] =>[orig_patent_app_number] => 12835706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8810381 [patent_doc_number] => 08448048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Flash memory device and related programming method' [patent_app_type] => utility [patent_app_number] => 12/769692 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8487 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12769692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6463685 [patent_doc_number] => 20100281342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'MEMORY CONTROLLER AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/768047 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281342.pdf [firstpage_image] =>[orig_patent_app_number] => 12768047 [rel_patent_id] =>[rel_patent_doc_number] =>)