Application number | Title of the application | Filing Date | Status |
---|
08/540218 | DATA PROCESSING SYSTEM WITH AN ENHANCED CACHE MEMORY CONTROL | Oct 5, 1995 | Abandoned |
Array
(
[id] => 3700456
[patent_doc_number] => 05696939
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Apparatus and method using a semaphore buffer for semaphore instructions'
[patent_app_type] => 1
[patent_app_number] => 8/536534
[patent_app_country] => US
[patent_app_date] => 1995-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1986
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696939.pdf
[firstpage_image] =>[orig_patent_app_number] => 536534
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/536534 | Apparatus and method using a semaphore buffer for semaphore instructions | Sep 28, 1995 | Issued |
Array
(
[id] => 3518562
[patent_doc_number] => 05515514
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Peripheral processor card for upgrading a computer'
[patent_app_type] => 1
[patent_app_number] => 8/535761
[patent_app_country] => US
[patent_app_date] => 1995-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8959
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/515/05515514.pdf
[firstpage_image] =>[orig_patent_app_number] => 535761
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/535761 | Peripheral processor card for upgrading a computer | Sep 27, 1995 | Issued |
Array
(
[id] => 3765745
[patent_doc_number] => 05802589
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Data buffering apparatus for buffering imaging data between a raster image processor (RIP) and an output device'
[patent_app_type] => 1
[patent_app_number] => 8/534908
[patent_app_country] => US
[patent_app_date] => 1995-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3614
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/802/05802589.pdf
[firstpage_image] =>[orig_patent_app_number] => 534908
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/534908 | Data buffering apparatus for buffering imaging data between a raster image processor (RIP) and an output device | Sep 27, 1995 | Issued |
08/519434 | METHOD FOR FINDING A RESOURCE IN A SCALABLE DISTRIBUTED COMPUTING ENVIRONMENT | Aug 27, 1995 | Abandoned |
Array
(
[id] => 3627279
[patent_doc_number] => 05535418
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Information processing system with selection of input/output processing control according to precalculated input/output processing time'
[patent_app_type] => 1
[patent_app_number] => 8/517654
[patent_app_country] => US
[patent_app_date] => 1995-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2622
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/535/05535418.pdf
[firstpage_image] =>[orig_patent_app_number] => 517654
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/517654 | Information processing system with selection of input/output processing control according to precalculated input/output processing time | Aug 21, 1995 | Issued |
Array
(
[id] => 3841647
[patent_doc_number] => 05784586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Addressing method for executing load instructions out of order with respect to store instructions'
[patent_app_type] => 1
[patent_app_number] => 8/517229
[patent_app_country] => US
[patent_app_date] => 1995-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3956
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784586.pdf
[firstpage_image] =>[orig_patent_app_number] => 517229
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/517229 | Addressing method for executing load instructions out of order with respect to store instructions | Aug 20, 1995 | Issued |
Array
(
[id] => 3848332
[patent_doc_number] => 05740414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Method and apparatus for coordinating the use of physical registers in a microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/516230
[patent_app_country] => US
[patent_app_date] => 1995-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7110
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740414.pdf
[firstpage_image] =>[orig_patent_app_number] => 516230
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/516230 | Method and apparatus for coordinating the use of physical registers in a microprocessor | Aug 16, 1995 | Issued |
Array
(
[id] => 3601104
[patent_doc_number] => 05517616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-14
[patent_title] => 'Multi-processor computer system with system monitoring by each processor and exchange of system status information between individual processors'
[patent_app_type] => 1
[patent_app_number] => 8/509418
[patent_app_country] => US
[patent_app_date] => 1995-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1785
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/517/05517616.pdf
[firstpage_image] =>[orig_patent_app_number] => 509418
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/509418 | Multi-processor computer system with system monitoring by each processor and exchange of system status information between individual processors | Jul 30, 1995 | Issued |
Array
(
[id] => 3744958
[patent_doc_number] => 05694553
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Method and apparatus for determining the dispatch readiness of buffered load operations in a processor'
[patent_app_type] => 1
[patent_app_number] => 8/508233
[patent_app_country] => US
[patent_app_date] => 1995-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 8498
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694553.pdf
[firstpage_image] =>[orig_patent_app_number] => 508233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/508233 | Method and apparatus for determining the dispatch readiness of buffered load operations in a processor | Jul 26, 1995 | Issued |
Array
(
[id] => 3898158
[patent_doc_number] => 05748909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Interface board and instruction processing device without a local CPU'
[patent_app_type] => 1
[patent_app_number] => 8/504830
[patent_app_country] => US
[patent_app_date] => 1995-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 8097
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748909.pdf
[firstpage_image] =>[orig_patent_app_number] => 504830
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/504830 | Interface board and instruction processing device without a local CPU | Jul 19, 1995 | Issued |
Array
(
[id] => 3918686
[patent_doc_number] => 05752003
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Architecture for managing traffic in a virtual LAN environment'
[patent_app_type] => 1
[patent_app_number] => 8/502835
[patent_app_country] => US
[patent_app_date] => 1995-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5595
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/752/05752003.pdf
[firstpage_image] =>[orig_patent_app_number] => 502835
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/502835 | Architecture for managing traffic in a virtual LAN environment | Jul 13, 1995 | Issued |
Array
(
[id] => 3633449
[patent_doc_number] => 05615351
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Method and system for correlating usage data in a distributed architecture'
[patent_app_type] => 1
[patent_app_number] => 8/499334
[patent_app_country] => US
[patent_app_date] => 1995-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2119
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/615/05615351.pdf
[firstpage_image] =>[orig_patent_app_number] => 499334
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/499334 | Method and system for correlating usage data in a distributed architecture | Jul 6, 1995 | Issued |
Array
(
[id] => 3673616
[patent_doc_number] => 05649178
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Apparatus and method for storing and initializing branch prediction with selective information transfer'
[patent_app_type] => 1
[patent_app_number] => 8/474017
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3881
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/649/05649178.pdf
[firstpage_image] =>[orig_patent_app_number] => 474017
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/474017 | Apparatus and method for storing and initializing branch prediction with selective information transfer | Jun 6, 1995 | Issued |
08/472360 | METHOD AND SYSTEM IN A DATA PROCESSING SYSTEM FOR EFFICIENTLY FETCHINGINSTRUCTIONS USING MUTIPLE PREFETCH ELEMENTS CAPABLE OF FETCHING MULTIPLE INSTRUCTIONS | Jun 6, 1995 | Abandoned |
08/483659 | MICROCOMPUTER SYSTEM WITH EXTERNAL INTERFACE CAPABILITY FOR DIGITAL SIGNAL PROCESSING | Jun 6, 1995 | Abandoned |
Array
(
[id] => 3788064
[patent_doc_number] => 05774686
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Method and apparatus for providing two system architectures in a processor'
[patent_app_type] => 1
[patent_app_number] => 8/482239
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 10526
[patent_no_of_claims] => 66
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774686.pdf
[firstpage_image] =>[orig_patent_app_number] => 482239
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/482239 | Method and apparatus for providing two system architectures in a processor | Jun 6, 1995 | Issued |
Array
(
[id] => 3625490
[patent_doc_number] => 05566310
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Computer program product for improving 3270 data stream performance by reducing transmission traffic'
[patent_app_type] => 1
[patent_app_number] => 8/488029
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 12976
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/566/05566310.pdf
[firstpage_image] =>[orig_patent_app_number] => 488029
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/488029 | Computer program product for improving 3270 data stream performance by reducing transmission traffic | Jun 6, 1995 | Issued |
Array
(
[id] => 3895616
[patent_doc_number] => 05826111
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Modem employing digital signal processor'
[patent_app_type] => 1
[patent_app_number] => 8/490445
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 32
[patent_no_of_words] => 23484
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/826/05826111.pdf
[firstpage_image] =>[orig_patent_app_number] => 490445
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/490445 | Modem employing digital signal processor | Jun 6, 1995 | Issued |
Array
(
[id] => 3603279
[patent_doc_number] => 05586267
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Apparatus for providing for automatic topology discovery in an ATM network or the like'
[patent_app_type] => 1
[patent_app_number] => 8/484656
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 56
[patent_no_of_words] => 20606
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/586/05586267.pdf
[firstpage_image] =>[orig_patent_app_number] => 484656
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484656 | Apparatus for providing for automatic topology discovery in an ATM network or the like | Jun 6, 1995 | Issued |