
Hai Phan
Supervisory Patent Examiner (ID: 6233, Phone: (571)272-6338 , Office: P/2685 )
| Most Active Art Unit | 2614 |
| Art Unit(s) | 2654, 2685, 2614, 2734 |
| Total Applications | 530 |
| Issued Applications | 277 |
| Pending Applications | 96 |
| Abandoned Applications | 160 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6595463
[patent_doc_number] => 20020042199
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-11
[patent_title] => 'Polishing by CMP for optimized planarization'
[patent_app_type] => new
[patent_app_number] => 09/956680
[patent_app_country] => US
[patent_app_date] => 2001-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2580
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[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20020042199.pdf
[firstpage_image] =>[orig_patent_app_number] => 09956680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/956680 | Polishing by CMP for optimized planarization | Sep 19, 2001 | Abandoned |
Array
(
[id] => 6838935
[patent_doc_number] => 20030036275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-20
[patent_title] => 'METHOD FOR FORMING INTEGRATED CIRCUIT HAVING MONOS DEVICE AND MIXED-SIGNAL CIRCUIT'
[patent_app_type] => new
[patent_app_number] => 09/930998
[patent_app_country] => US
[patent_app_date] => 2001-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3127
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[pdf_file] => publications/A1/0036/20030036275.pdf
[firstpage_image] =>[orig_patent_app_number] => 09930998
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/930998 | Method for forming integrated circuit having MONOS device and mixed-signal circuit | Aug 16, 2001 | Issued |
Array
(
[id] => 6409417
[patent_doc_number] => 20020182864
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-05
[patent_title] => 'Etching process'
[patent_app_type] => new
[patent_app_number] => 09/888846
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0182/20020182864.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888846
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888846 | Etching process | Jun 24, 2001 | Abandoned |
Array
(
[id] => 6894059
[patent_doc_number] => 20010016425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'Semiconductor processing methods, methods of forming hemispherical grain polysilicon, methods of forming capacitors, and methods of forming wordlines'
[patent_app_type] => new
[patent_app_number] => 09/751213
[patent_app_country] => US
[patent_app_date] => 2000-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3134
[patent_no_of_claims] => 32
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[pdf_file] => publications/A1/0016/20010016425.pdf
[firstpage_image] =>[orig_patent_app_number] => 09751213
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/751213 | Semiconductor processing methods, methods of forming hemispherical grain polysilicon, methods of forming capacitors, and methods of forming wordlines | Dec 28, 2000 | Issued |
Array
(
[id] => 7026481
[patent_doc_number] => 20010013507
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-16
[patent_title] => 'Method for CMP of low dielectric constant polymer layers'
[patent_app_type] => new
[patent_app_number] => 09/742853
[patent_app_country] => US
[patent_app_date] => 2000-12-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0013/20010013507.pdf
[firstpage_image] =>[orig_patent_app_number] => 09742853
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/742853 | Method for CMP of low dielectric constant polymer layers | Dec 20, 2000 | Abandoned |
Array
(
[id] => 1532710
[patent_doc_number] => 06410449
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Method of processing a workpiece using an externally excited torroidal plasma source'
[patent_app_type] => B1
[patent_app_number] => 09/636436
[patent_app_country] => US
[patent_app_date] => 2000-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
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[pdf_file] => patents/06/410/06410449.pdf
[firstpage_image] =>[orig_patent_app_number] => 09636436
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/636436 | Method of processing a workpiece using an externally excited torroidal plasma source | Aug 10, 2000 | Issued |
Array
(
[id] => 1474663
[patent_doc_number] => 06387808
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[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Method of correcting topographical effects on a micro-electronic substrate'
[patent_app_type] => B1
[patent_app_number] => 09/620896
[patent_app_country] => US
[patent_app_date] => 2000-07-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/387/06387808.pdf
[firstpage_image] =>[orig_patent_app_number] => 09620896
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/620896 | Method of correcting topographical effects on a micro-electronic substrate | Jul 20, 2000 | Issued |
Array
(
[id] => 1536192
[patent_doc_number] => 06337277
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-08
[patent_title] => 'Clean chemistry low-k organic polymer etch'
[patent_app_type] => B1
[patent_app_number] => 09/606842
[patent_app_country] => US
[patent_app_date] => 2000-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 8303
[patent_no_of_claims] => 20
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[pdf_file] => patents/06/337/06337277.pdf
[firstpage_image] =>[orig_patent_app_number] => 09606842
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/606842 | Clean chemistry low-k organic polymer etch | Jun 27, 2000 | Issued |
Array
(
[id] => 1503679
[patent_doc_number] => 06465352
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Method for removing dry-etching residue in a semiconductor device fabricating process'
[patent_app_type] => B1
[patent_app_number] => 09/592523
[patent_app_country] => US
[patent_app_date] => 2000-06-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/592523 | Method for removing dry-etching residue in a semiconductor device fabricating process | Jun 11, 2000 | Issued |
Array
(
[id] => 1367878
[patent_doc_number] => 06566264
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-20
[patent_title] => 'Method for forming an opening in a semiconductor device substrate'
[patent_app_type] => B1
[patent_app_number] => 09/583970
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/566/06566264.pdf
[firstpage_image] =>[orig_patent_app_number] => 09583970
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/583970 | Method for forming an opening in a semiconductor device substrate | May 30, 2000 | Issued |
Array
(
[id] => 1440137
[patent_doc_number] => 06495462
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-17
[patent_title] => 'Components with releasable leads'
[patent_app_type] => B1
[patent_app_number] => 09/566273
[patent_app_country] => US
[patent_app_date] => 2000-05-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/566273 | Components with releasable leads | May 4, 2000 | Issued |
Array
(
[id] => 1486632
[patent_doc_number] => 06428721
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Polishing composition and polishing method employing it'
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[patent_app_number] => 09/564546
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[pdf_file] => patents/06/428/06428721.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/564546 | Polishing composition and polishing method employing it | May 3, 2000 | Issued |
Array
(
[id] => 1503674
[patent_doc_number] => 06465351
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Method of forming a capacitor lower electrode using a CMP stopping layer'
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Array
(
[id] => 1570328
[patent_doc_number] => 06498107
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[patent_issue_date] => 2002-12-24
[patent_title] => 'Interface control for film deposition by gas-cluster ion-beam processing'
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Array
(
[id] => 1446660
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[patent_title] => 'Ditch type floating ring for chemical mechanical polishing'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/547236 | Ditch type floating ring for chemical mechanical polishing | Apr 10, 2000 | Issued |
Array
(
[id] => 1566097
[patent_doc_number] => 06376377
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[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity'
[patent_app_type] => B1
[patent_app_number] => 09/541487
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[pdf_file] => patents/06/376/06376377.pdf
[firstpage_image] =>[orig_patent_app_number] => 09541487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/541487 | Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity | Apr 2, 2000 | Issued |
Array
(
[id] => 6473766
[patent_doc_number] => 20020022281
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[patent_title] => 'Convertible hot edge ring to improve low-k dielectric etch'
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Array
(
[id] => 1340110
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[patent_issue_date] => 2003-07-08
[patent_title] => 'Inter-layer connection structure, multilayer printed circuit board and production processes therefor'
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[patent_app_number] => 09/498222
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/498222 | Inter-layer connection structure, multilayer printed circuit board and production processes therefor | Feb 3, 2000 | Issued |
Array
(
[id] => 1347489
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[patent_title] => 'Cleaning brush conditioning apparatus'
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[firstpage_image] =>[orig_patent_app_number] => 09490912
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/490912 | Cleaning brush conditioning apparatus | Jan 24, 2000 | Issued |
Array
(
[id] => 4304347
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[patent_title] => 'Plasma pretreatment of photoresist in an oxide etch process'
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[patent_app_number] => 9/440792
[patent_app_country] => US
[patent_app_date] => 1999-11-15
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[pdf_file] => patents/06/326/06326307.pdf
[firstpage_image] =>[orig_patent_app_number] => 440792
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/440792 | Plasma pretreatment of photoresist in an oxide etch process | Nov 14, 1999 | Issued |