Search

Hai Phan

Examiner (ID: 15555)

Most Active Art Unit
2614
Art Unit(s)
2734, 2685, 2654, 2614
Total Applications
532
Issued Applications
277
Pending Applications
99
Abandoned Applications
159

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11062611 [patent_doc_number] => 20160259573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'VIRTUAL TAPE STORAGE USING INTER-PARTITION LOGICAL VOLUME COPIES' [patent_app_type] => utility [patent_app_number] => 14/636869 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5306 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636869 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/636869
VIRTUAL TAPE STORAGE USING INTER-PARTITION LOGICAL VOLUME COPIES Mar 2, 2015 Abandoned
Array ( [id] => 11062612 [patent_doc_number] => 20160259574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'INCREMENTAL REPLICATION OF A SOURCE DATA SET' [patent_app_type] => utility [patent_app_number] => 14/637151 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637151
Incremental replication of a source data set Mar 2, 2015 Issued
Array ( [id] => 10183958 [patent_doc_number] => 09213637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-15 [patent_title] => 'Read and write performance for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/613345 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12112 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14613345 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/613345
Read and write performance for non-volatile memory Feb 2, 2015 Issued
Array ( [id] => 10150849 [patent_doc_number] => 09183141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Method and apparatus for parallel transfer of blocks of data between an interface module and a non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 14/516133 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516133
Method and apparatus for parallel transfer of blocks of data between an interface module and a non-volatile semiconductor memory Oct 15, 2014 Issued
Array ( [id] => 11958074 [patent_doc_number] => 20170262226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/504127 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 26349 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15504127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/504127
Semiconductor integrated circuit apparatus Sep 2, 2014 Issued
Array ( [id] => 10098615 [patent_doc_number] => 09134927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Parallel block allocation for declustered logical disks' [patent_app_type] => utility [patent_app_number] => 14/468666 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468666 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/468666
Parallel block allocation for declustered logical disks Aug 25, 2014 Issued
Array ( [id] => 11830712 [patent_doc_number] => 09727454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Memory controller that provides addresses to host for memory location matching state tracked by memory controller' [patent_app_type] => utility [patent_app_number] => 14/466167 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 28127 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466167 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466167
Memory controller that provides addresses to host for memory location matching state tracked by memory controller Aug 21, 2014 Issued
Array ( [id] => 13639175 [patent_doc_number] => 09846546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Method and apparatus for storing image [patent_app_type] => utility [patent_app_number] => 14/893659 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5838 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14893659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/893659
Method and apparatus for storing image Jun 16, 2014 Issued
Array ( [id] => 13110257 [patent_doc_number] => 10073782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Memory unit for data memory references of multi-threaded processor with interleaved inter-thread pipeline in emulated shared memory architectures [patent_app_type] => utility [patent_app_number] => 14/892446 [patent_app_country] => US [patent_app_date] => 2014-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6275 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14892446 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/892446
Memory unit for data memory references of multi-threaded processor with interleaved inter-thread pipeline in emulated shared memory architectures May 20, 2014 Issued
Array ( [id] => 11423264 [patent_doc_number] => 20170031408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SWITCHES COUPLING VOLATILE MEMORY DEVICES TO A POWER SOURCE' [patent_app_type] => utility [patent_app_number] => 15/303472 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15303472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/303472
Switches coupling volatile memory devices to a power source Apr 28, 2014 Issued
Array ( [id] => 11005973 [patent_doc_number] => 20160202923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'APPLICATION BACKUP AND RESTORE' [patent_app_type] => utility [patent_app_number] => 14/893250 [patent_app_country] => US [patent_app_date] => 2014-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14893250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/893250
Method and apparatus for backing up and restoring cross-virtual machine application Apr 10, 2014 Issued
Array ( [id] => 9599046 [patent_doc_number] => 20140195727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'APPARATUS AND METHOD FOR GENERATING DESCRIPTORS TO REACCESS A NON-VOLATILE SEMICONDUCTOR MEMORY OF A STORAGE DRIVE DUE TO AN ERROR' [patent_app_type] => utility [patent_app_number] => 14/208814 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 18260 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14208814 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/208814
Apparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error Mar 12, 2014 Issued
Array ( [id] => 10335447 [patent_doc_number] => 20150220452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'System, Method and Computer-Readable Medium for Dynamically Mapping a Non-Volatile Memory Store' [patent_app_type] => utility [patent_app_number] => 14/192683 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192683 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192683
System, method and computer-readable medium for dynamically mapping a non-volatile memory store Feb 26, 2014 Issued
Array ( [id] => 9563865 [patent_doc_number] => 20140181578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'METHOD AND APPARATUS FOR SLICE PARTIAL REBUILDING IN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 14/192098 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 20146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192098
Method and apparatus for slice partial rebuilding in a dispersed storage network Feb 26, 2014 Issued
Array ( [id] => 13919559 [patent_doc_number] => 10203902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Techniques for dynamically aligning a partition with a block size boundary [patent_app_type] => utility [patent_app_number] => 14/190821 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9863 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190821 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190821
Techniques for dynamically aligning a partition with a block size boundary Feb 25, 2014 Issued
Array ( [id] => 10358352 [patent_doc_number] => 20150243357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'Independent Ordering of Independent Threads' [patent_app_type] => utility [patent_app_number] => 14/191163 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2014 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191163 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/191163
Method and apparatus for memory access management Feb 25, 2014 Issued
Array ( [id] => 11924492 [patent_doc_number] => 09792075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-17 [patent_title] => 'Systems and methods for synthesizing virtual hard drives' [patent_app_type] => utility [patent_app_number] => 14/191362 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191362 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/191362
Systems and methods for synthesizing virtual hard drives Feb 25, 2014 Issued
Array ( [id] => 10358355 [patent_doc_number] => 20150243360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'METHOD, APPARATUS AND DEVICE FOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 14/190804 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6015 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190804 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190804
Method, apparatus and device for data processing for determining a predetermined state of a memory Feb 25, 2014 Issued
Array ( [id] => 10357134 [patent_doc_number] => 20150242139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'SYSTEM AND METHOD FOR TRANSPOSED STORAGE IN RAID ARRAYS' [patent_app_type] => utility [patent_app_number] => 14/188347 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188347 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188347
System and method for transposed storage in raid arrays Feb 23, 2014 Issued
Array ( [id] => 10543583 [patent_doc_number] => 09268715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'System and method for validation of cache memory locking' [patent_app_type] => utility [patent_app_number] => 14/188650 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188650 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188650
System and method for validation of cache memory locking Feb 23, 2014 Issued
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