Hai Vo

Array ( [id] => 11328436 [patent_doc_number] => 20160359048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/240332 [patent_app_country] => US [patent_app_date] => 2016-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 19925 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15240332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13392551 [patent_doc_number] => 20180247818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => AUTOMATIC INSPECTION DEVICE AND METHOD OF LASER PROCESSING EQUIPMENT [patent_app_type] => utility [patent_app_number] => 15/757500 [patent_app_country] => US [patent_app_date] => 2016-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15757500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13019171 [patent_doc_number] => 10032703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Package-on-package semiconductor assemblies and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/229668 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3333 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11273723 [patent_doc_number] => 20160336271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 15/220270 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17107659 [patent_doc_number] => 11127887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Semiconductor light emitting device with reflective side coating [patent_app_type] => utility [patent_app_number] => 15/750144 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 5085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15750144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11453315 [patent_doc_number] => 09576967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-21 [patent_title] => 'Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings' [patent_app_type] => utility [patent_app_number] => 15/198175 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 50 [patent_no_of_words] => 14663 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12457158 [patent_doc_number] => 09984923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Barrier layers in trenches and vias [patent_app_type] => utility [patent_app_number] => 15/198516 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4345 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11615528 [patent_doc_number] => 09653391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Semiconductor packaging structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/198286 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11732902 [patent_doc_number] => 20170194345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/198135 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14125465 [patent_doc_number] => 10249596 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-02 [patent_title] => Fan-out in ball grid array (BGA) package [patent_app_type] => utility [patent_app_number] => 15/198253 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11096694 [patent_doc_number] => 20160293663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'DISPLAY PANEL FOR COMPENSATING NEGATIVE POWER SUPPLY VOLTAGE, DISPLAY MODULE AND MOBILE DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/187438 [patent_app_country] => US [patent_app_date] => 2016-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11096589 [patent_doc_number] => 20160293558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring' [patent_app_type] => utility [patent_app_number] => 15/177081 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3745 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11096637 [patent_doc_number] => 20160293606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/175190 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 25547 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12872395 [patent_doc_number] => 20180182640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR ELEMENT COMPRISING A LAYER FOR TRAPPING CHARGES [patent_app_type] => utility [patent_app_number] => 15/577133 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15577133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12113923 [patent_doc_number] => 09869911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Display apparatus having a driver disposed on a flexible substrate and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/156749 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7936 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15156749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13754737 [patent_doc_number] => 10170320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Feature fill with multi-stage nucleation inhibition [patent_app_type] => utility [patent_app_number] => 15/156129 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 14580 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15156129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11746771 [patent_doc_number] => 20170200844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'Method For Manufacturing Crystalline Silicon Solar Cell Modules' [patent_app_type] => utility [patent_app_number] => 15/155713 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4945 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11417627 [patent_doc_number] => 09564460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-07 [patent_title] => 'Thin-film transistor and its manufacturing method, array substrate and display device' [patent_app_type] => utility [patent_app_number] => 15/155403 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4232 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12214933 [patent_doc_number] => 09911751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Manufacturing method for semiconductor device having hole penetrating stack structure' [patent_app_type] => utility [patent_app_number] => 15/155937 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6827 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11057184 [patent_doc_number] => 20160254146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'Methods and structures for preparing single crystal silicon wafers for use as substrates for epitaxial growth of crack-free gallium nitride films and devices' [patent_app_type] => utility [patent_app_number] => 15/149190 [patent_app_country] => US [patent_app_date] => 2016-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15149190 [rel_patent_id] =>[rel_patent_doc_number] =>)