Hai Vo

Array ( [id] => 19208009 [patent_doc_number] => 20240179908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/353621 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19714534 [patent_doc_number] => 20250024676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE HAVING CONTROLLED LATERAL ISOLATION TRENCH DEPTH AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/349527 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18898672 [patent_doc_number] => 20240014157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => NONVOLATILE MEMORY DEVICE, SYSTEM INCLUDING THE SAME AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/349017 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18743460 [patent_doc_number] => 20230352448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF DIELECTRIC MATERIALS BETWEEN SEMICONDUCTOR DIES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/346692 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19688097 [patent_doc_number] => 20250006642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => CHIPLET-TO-CHIPLET PROTOCOL SWITCH [patent_app_type] => utility [patent_app_number] => 18/345867 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19690191 [patent_doc_number] => 20250008736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BACKSIDE SEMICONDUCTOR SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/343118 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20734516 [patent_doc_number] => 12641781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Three-dimensional NAND memory device and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/340086 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20435971 [patent_doc_number] => 12507452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device [patent_app_type] => utility [patent_app_number] => 18/340278 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5681 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19648475 [patent_doc_number] => 20240422995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => DYNAMIC RANDOM-ACCESS MEMORY (DRAM) ON HOT COMPUTE LOGIC FOR LAST-LEVEL-CACHE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/336775 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18696453 [patent_doc_number] => 20230326892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => DRAM MEMORY DEVICE WITH XTACKING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/336097 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18833822 [patent_doc_number] => 20230402349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE HAVING VIAS AND PADS FORMED BY LASER [patent_app_type] => utility [patent_app_number] => 18/335923 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18696421 [patent_doc_number] => 20230326860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY [patent_app_type] => utility [patent_app_number] => 18/206539 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18679997 [patent_doc_number] => 20230317655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MEMORY DEVICE INCLUDING MEMORY CHIP AND PERIPHERAL MEMORY CHIP AND METHOD OF MANUFACTURING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/328359 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18868088 [patent_doc_number] => 20230422525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR PACKAGE HAVING A THICK LOGIC DIE [patent_app_type] => utility [patent_app_number] => 18/203666 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20523393 [patent_doc_number] => 20260047507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => SYSTEMS AND METHODS FOR MASSIVELY PARALLEL CHIP INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/324884 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20418325 [patent_doc_number] => 12501629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Three-dimensional semiconductor memory device and electronic system including the same [patent_app_type] => utility [patent_app_number] => 18/323440 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 9324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20418325 [patent_doc_number] => 12501629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Three-dimensional semiconductor memory device and electronic system including the same [patent_app_type] => utility [patent_app_number] => 18/323440 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 9324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19604849 [patent_doc_number] => 20240395729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => CHIP PACKAGE STRUCTURE AND METHOD FOR PREVENTING WARPAGE OF CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/202057 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18823137 [patent_doc_number] => 20230397478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => ELECTRICAL PLANARIZATION OF CARBON NANOTUBE THIN FILMS FOR ELECTRONIC DEVICE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/199513 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18959091 [patent_doc_number] => 20240047418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/199553 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199553 [rel_patent_id] =>[rel_patent_doc_number] =>)