
Hajar Kolahdouzan
Examiner (ID: 11406, Phone: (571)270-5842 , Office: P/2898 )
| Most Active Art Unit | 2898 |
| Art Unit(s) | 4166, 2893, 2898 |
| Total Applications | 435 |
| Issued Applications | 302 |
| Pending Applications | 52 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9905903
[patent_doc_number] => 20150061102
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[patent_title] => 'ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF'
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Array
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Array
(
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[patent_issue_date] => 2019-11-05
[patent_title] => Multi-chip silicon substrate-less chip packaging
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Array
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[patent_title] => Semiconductor manufacturing apparatus and method of manufacturing semiconductor device
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Array
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Array
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Array
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[patent_title] => 'MIXED IMPEDANCE LEADS FOR DIE PACKAGES AND METHOD OF MAKING THE SAME'
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Array
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Array
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[patent_title] => Apparatus for radiation detection in a radiography imaging system
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Array
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[patent_title] => 'STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS'
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Array
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Array
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Array
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Array
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