Search

Hajar Kolahdouzan

Examiner (ID: 11406, Phone: (571)270-5842 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
4166, 2893, 2898
Total Applications
435
Issued Applications
302
Pending Applications
52
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9905903 [patent_doc_number] => 20150061102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/470159 [patent_app_country] => US [patent_app_date] => 2014-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7215 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14470159 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/470159
Electronic device package and fabrication method thereof Aug 26, 2014 Issued
Array ( [id] => 9905743 [patent_doc_number] => 20150060943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/470164 [patent_app_country] => US [patent_app_date] => 2014-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 67 [patent_no_of_words] => 29501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14470164 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/470164
NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATING THE SAME Aug 26, 2014 Abandoned
Array ( [id] => 15077703 [patent_doc_number] => 10468351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Multi-chip silicon substrate-less chip packaging [patent_app_type] => utility [patent_app_number] => 14/469500 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4579 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14469500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/469500
Multi-chip silicon substrate-less chip packaging Aug 25, 2014 Issued
Array ( [id] => 13242811 [patent_doc_number] => 10134612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Semiconductor manufacturing apparatus and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 14/467406 [patent_app_country] => US [patent_app_date] => 2014-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4723 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467406
Semiconductor manufacturing apparatus and method of manufacturing semiconductor device Aug 24, 2014 Issued
Array ( [id] => 10703219 [patent_doc_number] => 20160049366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'INTEGRATED CIRCUITS WITH ELECTRONIC FUSE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/459607 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459607 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459607
Integrated circuits with electronic fuse structures Aug 13, 2014 Issued
Array ( [id] => 10244919 [patent_doc_number] => 20150129914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'LIGHT-EMITTING DIODE PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/340491 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3191 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340491
LIGHT-EMITTING DIODE PACKAGE Jul 23, 2014 Abandoned
Array ( [id] => 11353662 [patent_doc_number] => 20160372402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'MIXED IMPEDANCE LEADS FOR DIE PACKAGES AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/902194 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4454 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902194 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/902194
Mixed impedance leads for die packages and method of making the same Jul 1, 2014 Issued
Array ( [id] => 11353960 [patent_doc_number] => 20160372700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING SAME' [patent_app_type] => utility [patent_app_number] => 14/901739 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12116 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14901739 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/901739
Optoelectronic component and method for producing same Jun 29, 2014 Issued
Array ( [id] => 15077899 [patent_doc_number] => 10468450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Apparatus for radiation detection in a radiography imaging system [patent_app_type] => utility [patent_app_number] => 14/245200 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14245200 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/245200
Apparatus for radiation detection in a radiography imaging system Apr 3, 2014 Issued
Array ( [id] => 10394821 [patent_doc_number] => 20150279828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/231101 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4319 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231101 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/231101
Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods Mar 30, 2014 Issued
Array ( [id] => 10370375 [patent_doc_number] => 20150255380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/230865 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5111 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230865 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230865
Package structure Mar 30, 2014 Issued
Array ( [id] => 10068415 [patent_doc_number] => 09107290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-11 [patent_title] => 'Package structure and stacked package module with the same' [patent_app_type] => utility [patent_app_number] => 14/230941 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230941 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230941
Package structure and stacked package module with the same Mar 30, 2014 Issued
Array ( [id] => 10409860 [patent_doc_number] => 20150294869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'METHOD FOR MANUFACTURING LOW-TEMPERATURE POLYSILICON THIN FILM TRANSISTOR AND ARRAY SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/436142 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14436142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/436142
METHOD FOR MANUFACTURING LOW-TEMPERATURE POLYSILICON THIN FILM TRANSISTOR AND ARRAY SUBSTRATE Mar 30, 2014 Abandoned
Array ( [id] => 10315143 [patent_doc_number] => 20150200146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes' [patent_app_type] => utility [patent_app_number] => 14/153417 [patent_app_country] => US [patent_app_date] => 2014-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6449 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14153417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/153417
Semiconductor manufacturing using disposable test circuitry within scribe lanes Jan 12, 2014 Issued
Array ( [id] => 11207842 [patent_doc_number] => 09437473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Method for separating at least two substrates along a selected interface' [patent_app_type] => utility [patent_app_number] => 14/424311 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14424311 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/424311
Method for separating at least two substrates along a selected interface Sep 3, 2013 Issued
Array ( [id] => 10631488 [patent_doc_number] => 09349644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Semiconductor device producing method' [patent_app_type] => utility [patent_app_number] => 14/424118 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6707 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14424118 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/424118
Semiconductor device producing method Sep 2, 2013 Issued
Array ( [id] => 9145379 [patent_doc_number] => 20130299902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/943143 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3516 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943143
FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE Jul 15, 2013 Abandoned
Array ( [id] => 10158572 [patent_doc_number] => 09190356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Semiconductor devices with close-packed via structures having in-plane routing and method of making same' [patent_app_type] => utility [patent_app_number] => 14/384606 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5000 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14384606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/384606
Semiconductor devices with close-packed via structures having in-plane routing and method of making same Mar 11, 2013 Issued
Array ( [id] => 10158572 [patent_doc_number] => 09190356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Semiconductor devices with close-packed via structures having in-plane routing and method of making same' [patent_app_type] => utility [patent_app_number] => 14/384606 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5000 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14384606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/384606
Semiconductor devices with close-packed via structures having in-plane routing and method of making same Mar 11, 2013 Issued
Array ( [id] => 9809807 [patent_doc_number] => 20150021752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/374143 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7829 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14374143 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/374143
Semiconductor device Mar 11, 2013 Issued
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