Hamdy S. Ahmed

Array ( [id] => 7106774 [patent_doc_number] => 20050108301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method for balancing wear when writing data in a flash memory' [patent_app_type] => utility [patent_app_number] => 10/841578 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2213 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108301.pdf [firstpage_image] =>[orig_patent_app_number] => 10841578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7071190 [patent_doc_number] => 20050246575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Minimizing system downtime through intelligent data caching in an appliance-based business continuance architecture' [patent_app_type] => utility [patent_app_number] => 10/835299 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6110 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20050246575.pdf [firstpage_image] =>[orig_patent_app_number] => 10835299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4576475 [patent_doc_number] => 07822929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Two-hop cache coherency protocol' [patent_app_type] => utility [patent_app_number] => 10/833963 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5445 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/822/07822929.pdf [firstpage_image] =>[orig_patent_app_number] => 10833963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 332935 [patent_doc_number] => 07512759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 10/549028 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4571 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512759.pdf [firstpage_image] =>[orig_patent_app_number] => 10549028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6946598 [patent_doc_number] => 20050198435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Data storage array linking operation switching control system' [patent_app_type] => utility [patent_app_number] => 10/792973 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2901 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198435.pdf [firstpage_image] =>[orig_patent_app_number] => 10792973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5719455 [patent_doc_number] => 20060072228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Method and circuit for operating a storage device' [patent_app_type] => utility [patent_app_number] => 10/538626 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20060072228.pdf [firstpage_image] =>[orig_patent_app_number] => 10538626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7166751 [patent_doc_number] => 20050086424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Well-matched echo clock in memory system' [patent_app_type] => utility [patent_app_number] => 10/689954 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3274 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086424.pdf [firstpage_image] =>[orig_patent_app_number] => 10689954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7215132 [patent_doc_number] => 20050044448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'System and method for managing power consumption and data integrity in a computer system' [patent_app_type] => utility [patent_app_number] => 10/644427 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2874 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044448.pdf [firstpage_image] =>[orig_patent_app_number] => 10644427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7440316 [patent_doc_number] => 20040162954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Reformat logic to translate between a virtual address and a compressed physical address' [patent_app_type] => new [patent_app_number] => 10/632215 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5313 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20040162954.pdf [firstpage_image] =>[orig_patent_app_number] => 10632215 [rel_patent_id] =>[rel_patent_doc_number] =>)