Search

Hana Sanei Featherly

Examiner (ID: 12243)

Most Active Art Unit
2875
Art Unit(s)
2889, 2879, 2875
Total Applications
839
Issued Applications
566
Pending Applications
61
Abandoned Applications
223

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11875443 [patent_doc_number] => 09747217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Distributed history buffer flush and restore handling in a parallel slice design' [patent_app_type] => utility [patent_app_number] => 14/727531 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5438 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727531 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727531
Distributed history buffer flush and restore handling in a parallel slice design May 31, 2015 Issued
Array ( [id] => 16446936 [patent_doc_number] => 10838865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Stacked memory device system interconnect directory-based cache coherence methodology [patent_app_type] => utility [patent_app_number] => 14/706516 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4193 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706516
Stacked memory device system interconnect directory-based cache coherence methodology May 6, 2015 Issued
Array ( [id] => 10672993 [patent_doc_number] => 20160019138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'MEMORY MODULE AND SYSTEM AND METHOD OF OPERATION' [patent_app_type] => utility [patent_app_number] => 14/706873 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706873 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706873
Memory module having volatile and non-volatile memory subsystems and method of operation May 6, 2015 Issued
Array ( [id] => 10439266 [patent_doc_number] => 20150324279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'HYBRID MEMORY TABLE CLUSTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/706584 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2114 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706584
HYBRID MEMORY TABLE CLUSTER SYSTEM May 6, 2015 Abandoned
Array ( [id] => 11131354 [patent_doc_number] => 20160328329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'Distributed History Buffer Flush and Restore Handling in a Parallel Slice Design' [patent_app_type] => utility [patent_app_number] => 14/706815 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706815
Distributed history buffer flush and restore handling in a parallel slice design May 6, 2015 Issued
Array ( [id] => 16417596 [patent_doc_number] => 10825496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => In-memory lightweight memory coherence protocol [patent_app_type] => utility [patent_app_number] => 14/706490 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706490 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706490
In-memory lightweight memory coherence protocol May 6, 2015 Issued
Array ( [id] => 11131187 [patent_doc_number] => 20160328162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'LOGICAL ARRAYS RUNNING ON PHYSICAL HARDWARE WHERE RESERVE PHYSICAL CAPACITY IS AVAILABLE' [patent_app_type] => utility [patent_app_number] => 14/706760 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706760 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706760
LOGICAL ARRAYS RUNNING ON PHYSICAL HARDWARE WHERE RESERVE PHYSICAL CAPACITY IS AVAILABLE May 6, 2015 Abandoned
Array ( [id] => 11131347 [patent_doc_number] => 20160328322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'PROCESSOR TO MEMORY BYPASS' [patent_app_type] => utility [patent_app_number] => 14/705506 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705506 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705506
Processor to memory with coherency bypass May 5, 2015 Issued
Array ( [id] => 14856801 [patent_doc_number] => 10417128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Memory coherence in a multi-core, multi-level, heterogeneous computer architecture implementing hardware-managed and software managed caches [patent_app_type] => utility [patent_app_number] => 14/705806 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705806 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705806
Memory coherence in a multi-core, multi-level, heterogeneous computer architecture implementing hardware-managed and software managed caches May 5, 2015 Issued
Array ( [id] => 11124205 [patent_doc_number] => 20160321179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'ENFORCING DATA PROTECTION IN AN INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 14/700259 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5634 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700259 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700259
Enforcing data protection in an interconnect Apr 29, 2015 Issued
Array ( [id] => 15012785 [patent_doc_number] => 10452538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Determining task scores reflective of memory access statistics in NUMA systems [patent_app_type] => utility [patent_app_number] => 14/602109 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602109 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602109
Determining task scores reflective of memory access statistics in NUMA systems Jan 20, 2015 Issued
Array ( [id] => 11013108 [patent_doc_number] => 20160210061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'ARCHITECTURE FOR A TRANSPARENTLY-SCALABLE, ULTRA-HIGH-THROUGHPUT STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 14/602016 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602016 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602016
ARCHITECTURE FOR A TRANSPARENTLY-SCALABLE, ULTRA-HIGH-THROUGHPUT STORAGE NETWORK Jan 20, 2015
Array ( [id] => 11013116 [patent_doc_number] => 20160210069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'Systems and Methods For Overriding Memory Access Permissions In A Virtual Machine' [patent_app_type] => utility [patent_app_number] => 14/601475 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11027 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601475 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601475
Systems and Methods For Overriding Memory Access Permissions In A Virtual Machine Jan 20, 2015
Array ( [id] => 11013278 [patent_doc_number] => 20160210231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'HETEROGENEOUS SYSTEM ARCHITECTURE FOR SHARED MEMORY' [patent_app_type] => utility [patent_app_number] => 14/601565 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6895 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601565
HETEROGENEOUS SYSTEM ARCHITECTURE FOR SHARED MEMORY Jan 20, 2015
Array ( [id] => 10327746 [patent_doc_number] => 20150212750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'DISK ARRAY APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/601393 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5852 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601393 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601393
Disk array apparatus, control method therefor, and storage medium Jan 20, 2015 Issued
Array ( [id] => 11013107 [patent_doc_number] => 20160210060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'DYNAMIC RESOURCE ALLOCATION WITHIN STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 14/601912 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10305 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601912
DYNAMIC RESOURCE ALLOCATION WITHIN STORAGE DEVICES Jan 20, 2015
Array ( [id] => 10416733 [patent_doc_number] => 20150301744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'MEMORY SYSTEM AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/601552 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601552
Memory system capable of controlling operation performance according to temperature and method of operating the same Jan 20, 2015 Issued
Array ( [id] => 11013289 [patent_doc_number] => 20160210241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'REDUCING A SIZE OF A LOGICAL TO PHYSICAL DATA ADDRESS TRANSLATION TABLE' [patent_app_type] => utility [patent_app_number] => 14/602092 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602092 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602092
REDUCING A SIZE OF A LOGICAL TO PHYSICAL DATA ADDRESS TRANSLATION TABLE Jan 20, 2015
Array ( [id] => 10764128 [patent_doc_number] => 20160110283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'ON-DEMAND EXPANSION OF SYNCHRONIZATION PRIMITIVES' [patent_app_type] => utility [patent_app_number] => 14/518995 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518995
ON-DEMAND EXPANSION OF SYNCHRONIZATION PRIMITIVES Oct 19, 2014 Abandoned
Array ( [id] => 11830728 [patent_doc_number] => 09727470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-08 [patent_title] => 'Using a local cache to store, access and modify files tiered to cloud storage' [patent_app_type] => utility [patent_app_number] => 14/501928 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13313 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501928 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501928
Using a local cache to store, access and modify files tiered to cloud storage Sep 29, 2014 Issued
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