
Hang Pan
Examiner (ID: 15129, Phone: (571)270-7667 , Office: P/2197 )
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2197, 2193 |
| Total Applications | 724 |
| Issued Applications | 507 |
| Pending Applications | 66 |
| Abandoned Applications | 166 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17645486
[patent_doc_number] => 20220173225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => Dummy Gate Cutting Process and Resulting Gate Structures
[patent_app_type] => utility
[patent_app_number] => 17/650942
[patent_app_country] => US
[patent_app_date] => 2022-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650942
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/650942 | Dummy gate cutting process and resulting gate structures | Feb 13, 2022 | Issued |
Array
(
[id] => 18828916
[patent_doc_number] => 11844217
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-12
[patent_title] => Methods for forming multi-layer vertical nor-type memory string arrays
[patent_app_type] => utility
[patent_app_number] => 17/669024
[patent_app_country] => US
[patent_app_date] => 2022-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 30
[patent_no_of_words] => 5309
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669024
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/669024 | Methods for forming multi-layer vertical nor-type memory string arrays | Feb 9, 2022 | Issued |
Array
(
[id] => 17615475
[patent_doc_number] => 20220157755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => Method and System for Packing Optimization of Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 17/588525
[patent_app_country] => US
[patent_app_date] => 2022-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8760
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588525
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/588525 | Method and system for packing optimization of semiconductor devices | Jan 30, 2022 | Issued |
Array
(
[id] => 17599581
[patent_doc_number] => 20220149155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => CORE-SHELL NANOSTRUCTURES FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/582866
[patent_app_country] => US
[patent_app_date] => 2022-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582866
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/582866 | Core-shell nanostructures for semiconductor devices | Jan 23, 2022 | Issued |
Array
(
[id] => 17986303
[patent_doc_number] => 20220352340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => GATE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/648202
[patent_app_country] => US
[patent_app_date] => 2022-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4681
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648202
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648202 | GATE STRUCTURE AND MANUFACTURING METHOD THEREOF | Jan 17, 2022 | Pending |
Array
(
[id] => 18514660
[patent_doc_number] => 20230230921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-20
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/577996
[patent_app_country] => US
[patent_app_date] => 2022-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9860
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577996
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/577996 | Semiconductor memory device and method for manufacturing the same | Jan 17, 2022 | Issued |
Array
(
[id] => 17583057
[patent_doc_number] => 20220139912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/577549
[patent_app_country] => US
[patent_app_date] => 2022-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8815
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577549
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/577549 | Method for fabricating semiconductor device | Jan 17, 2022 | Issued |
Array
(
[id] => 18857596
[patent_doc_number] => 11855193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Fin field-effect transistor device and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/648166
[patent_app_country] => US
[patent_app_date] => 2022-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 25
[patent_no_of_words] => 11882
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648166
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648166 | Fin field-effect transistor device and method of forming the same | Jan 16, 2022 | Issued |
Array
(
[id] => 18320510
[patent_doc_number] => 20230118638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => Epitaxy Regions With Reduced Loss Control
[patent_app_type] => utility
[patent_app_number] => 17/648010
[patent_app_country] => US
[patent_app_date] => 2022-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8413
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648010
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648010 | Epitaxy regions with reduced loss control | Jan 13, 2022 | Issued |
Array
(
[id] => 17583118
[patent_doc_number] => 20220139973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT
[patent_app_type] => utility
[patent_app_number] => 17/574312
[patent_app_country] => US
[patent_app_date] => 2022-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12282
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574312
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/574312 | Solid-state imaging device, method of manufacturing the same, and electronic equipment | Jan 11, 2022 | Issued |
Array
(
[id] => 17795841
[patent_doc_number] => 20220254933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-11
[patent_title] => ACTIVE DEVICE SUBSTRATE AND FABRICATION METHOD OF ACTIVE DEVICE SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/572662
[patent_app_country] => US
[patent_app_date] => 2022-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5171
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572662
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/572662 | Active device substrate and fabrication method of active device substrate | Jan 10, 2022 | Issued |
Array
(
[id] => 17566862
[patent_doc_number] => 20220131011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/571561
[patent_app_country] => US
[patent_app_date] => 2022-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18830
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571561
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/571561 | Semiconductor device and method of manufacturing the same | Jan 9, 2022 | Issued |
Array
(
[id] => 17566859
[patent_doc_number] => 20220131008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => INTEGRATED CIRCUIT DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/569952
[patent_app_country] => US
[patent_app_date] => 2022-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569952
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/569952 | Integrated circuit device | Jan 5, 2022 | Issued |
Array
(
[id] => 17566813
[patent_doc_number] => 20220130962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME
[patent_app_type] => utility
[patent_app_number] => 17/569376
[patent_app_country] => US
[patent_app_date] => 2022-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569376
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/569376 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME | Jan 4, 2022 | Abandoned |
Array
(
[id] => 18488420
[patent_doc_number] => 20230215768
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => OPTIMIZING STRESS IN A HYBRID VERTICAL-PFET AND HORIZONTAL-NFET NANOSHEET STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/566402
[patent_app_country] => US
[patent_app_date] => 2021-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5391
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566402
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/566402 | Optimizing stress in a hybrid vertical-PFET and horizontal-NFET nanosheet structure | Dec 29, 2021 | Issued |
Array
(
[id] => 18961195
[patent_doc_number] => 20240049522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/623193
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4280
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623193
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/623193 | Organic light-emitting diode display panel and display device | Dec 20, 2021 | Issued |
Array
(
[id] => 19008027
[patent_doc_number] => 20240072098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => DISPLAY DEVICE AND SPLICE DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/622982
[patent_app_country] => US
[patent_app_date] => 2021-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17622982
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/622982 | Display device and splice display device | Dec 19, 2021 | Issued |
Array
(
[id] => 18440246
[patent_doc_number] => 20230187541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => CROSS BAR VERTICAL FETS
[patent_app_type] => utility
[patent_app_number] => 17/644528
[patent_app_country] => US
[patent_app_date] => 2021-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644528
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/644528 | Cross bar vertical FETs | Dec 14, 2021 | Issued |
Array
(
[id] => 18440146
[patent_doc_number] => 20230187441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT FLYOVER STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/548027
[patent_app_country] => US
[patent_app_date] => 2021-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548027
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/548027 | INTEGRATED CIRCUIT STRUCTURES WITH TRENCH CONTACT FLYOVER STRUCTURE | Dec 9, 2021 | Pending |
Array
(
[id] => 17506679
[patent_doc_number] => 20220099782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => SYNCHRONIZATION OF UNSTABLE SIGNAL SOURCES FOR USE IN A PHASE STABLE INSTRUMENT
[patent_app_type] => utility
[patent_app_number] => 17/548381
[patent_app_country] => US
[patent_app_date] => 2021-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2073
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548381
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/548381 | Synchronization of unstable signal sources for use in a phase stable instrument | Dec 9, 2021 | Issued |