Search

Hanh N Nguyen

Examiner (ID: 8347, Phone: (571)272-2031 , Office: P/2834 )

Most Active Art Unit
2834
Art Unit(s)
2662, 2473, 2738, 2668, 2834, 2413, 2616, 2416, 2479
Total Applications
3179
Issued Applications
2551
Pending Applications
159
Abandoned Applications
469

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18348140 [patent_doc_number] => 20230136251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => ON-DEMAND DECODING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/146794 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146794
ON-DEMAND DECODING METHOD AND APPARATUS Dec 26, 2022 Pending
Array ( [id] => 18310005 [patent_doc_number] => 20230113905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/080680 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080680 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080680
Scan architecture for interconnect testing in 3D integrated circuits Dec 12, 2022 Issued
Array ( [id] => 18255797 [patent_doc_number] => 20230082836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => METHOD FOR PROVIDING ERROR DETECTION FOR A DISK DRIVE OF A SET TOP BOX [patent_app_type] => utility [patent_app_number] => 17/990861 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990861
METHOD FOR PROVIDING ERROR DETECTION FOR A DISK DRIVE OF A SET TOP BOX Nov 20, 2022 Pending
Array ( [id] => 18782779 [patent_doc_number] => 11824557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Transmitter and shortening method thereof [patent_app_type] => utility [patent_app_number] => 17/982000 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 28914 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982000
Transmitter and shortening method thereof Nov 6, 2022 Issued
Array ( [id] => 18833595 [patent_doc_number] => 20230402122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => Configurable Scan Chain Architecture for Multi-Port Memory [patent_app_type] => utility [patent_app_number] => 17/953271 [patent_app_country] => US [patent_app_date] => 2022-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953271
Configurable Scan Chain Architecture for Multi-Port Memory Sep 25, 2022 Pending
Array ( [id] => 18025210 [patent_doc_number] => 20220376709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/880144 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880144
Failure-tolerant error correction layout for memory sub-systems Aug 2, 2022 Issued
Array ( [id] => 18199786 [patent_doc_number] => 20230053306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => METHOD FOR LOSS REDUCTION IN A COMMUNICATION INTERFACE [patent_app_type] => utility [patent_app_number] => 17/873077 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873077
METHOD FOR LOSS REDUCTION IN A COMMUNICATION INTERFACE Jul 24, 2022 Pending
Array ( [id] => 18257395 [patent_doc_number] => 20230084435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => METHOD FOR TESTING MEMORY AND MEMORY TESTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/843588 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843588
METHOD FOR TESTING MEMORY AND MEMORY TESTING DEVICE Jun 16, 2022 Pending
Array ( [id] => 17884736 [patent_doc_number] => 20220300213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => High Speed Data Packet Flow Processing [patent_app_type] => utility [patent_app_number] => 17/835809 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835809
High speed data packet flow processing Jun 7, 2022 Issued
Array ( [id] => 18094703 [patent_doc_number] => 20220413044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Semiconductor device and method for generating test pulse signals [patent_app_type] => utility [patent_app_number] => 17/730243 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730243 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730243
Semiconductor device and method for generating test pulse signals Apr 26, 2022 Pending
Array ( [id] => 18334556 [patent_doc_number] => 20230126504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => DETECTION CIRCUIT AND DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/717142 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/717142
DETECTION CIRCUIT AND DETECTION METHOD Apr 10, 2022 Pending
Array ( [id] => 18827496 [patent_doc_number] => 11842785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Temperature-accelerated solid-state storage testing methods [patent_app_type] => utility [patent_app_number] => 17/716069 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716069
Temperature-accelerated solid-state storage testing methods Apr 7, 2022 Issued
Array ( [id] => 18631524 [patent_doc_number] => 20230290426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SCAN-BASED VOLTAGE FREQUENCY SCALING [patent_app_type] => utility [patent_app_number] => 17/692262 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692262
SCAN-BASED VOLTAGE FREQUENCY SCALING Mar 10, 2022 Pending
Array ( [id] => 18568385 [patent_doc_number] => 20230258721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => DELAY MEASUREMENT SYSTEM AND MEASUREMENT METHOD [patent_app_type] => utility [patent_app_number] => 17/671999 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671999
DELAY MEASUREMENT SYSTEM AND MEASUREMENT METHOD Feb 14, 2022 Pending
Array ( [id] => 17738896 [patent_doc_number] => 20220224358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => POLAR CODE DECODING APPARATUS AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/575598 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575598
POLAR CODE DECODING APPARATUS AND OPERATION METHOD THEREOF Jan 12, 2022 Pending
Array ( [id] => 18501254 [patent_doc_number] => 20230224079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR MEASURING DATA INTEGRITY IN TIME SENSITIVE NETWORKS [patent_app_type] => utility [patent_app_number] => 17/570422 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570422
METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR MEASURING DATA INTEGRITY IN TIME SENSITIVE NETWORKS Jan 6, 2022 Pending
Array ( [id] => 17979360 [patent_doc_number] => 11496242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Fast cyclic redundancy check: utilizing linearity of cyclic redundancy check for accelerating correction of corrupted network packets [patent_app_type] => utility [patent_app_number] => 17/556029 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6038 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556029
Fast cyclic redundancy check: utilizing linearity of cyclic redundancy check for accelerating correction of corrupted network packets Dec 19, 2021 Issued
Array ( [id] => 17677679 [patent_doc_number] => 20220190846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SINGLE ERROR CORRECT DOUBLE ERROR DETECT (SECDED) ERROR CODING WITH BURST ERROR DETECTION CAPABILITY [patent_app_type] => utility [patent_app_number] => 17/548176 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548176
SINGLE ERROR CORRECT DOUBLE ERROR DETECT (SECDED) ERROR CODING WITH BURST ERROR DETECTION CAPABILITY Dec 9, 2021 Pending
Array ( [id] => 17464653 [patent_doc_number] => 20220077959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => BROADCAST SIGNAL FRAME GENERATION DEVICE AND BROADCAST SIGNAL FRAME GENERATION METHOD USING BOUNDARY OF PHYSICAL LAYER PIPES OF CORE LAYER [patent_app_type] => utility [patent_app_number] => 17/527013 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527013
Broadcast signal frame generation device and broadcast signal frame generation method using boundary of physical layer pipes of core layer Nov 14, 2021 Issued
Array ( [id] => 17447914 [patent_doc_number] => 20220068419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => TEST CIRCUIT, TEST DEVICE AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/467570 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467570
TEST CIRCUIT, TEST DEVICE AND TEST METHOD THEREOF Sep 6, 2021 Pending
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