Search

Hanh N Nguyen

Examiner (ID: 8347, Phone: (571)272-2031 , Office: P/2834 )

Most Active Art Unit
2834
Art Unit(s)
2662, 2473, 2738, 2668, 2834, 2413, 2616, 2416, 2479
Total Applications
3179
Issued Applications
2551
Pending Applications
159
Abandoned Applications
469

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12093846 [patent_doc_number] => 20170350939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 15/171531 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12160 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15171531 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/171531
Scan architecture for interconnect testing in 3D integrated circuits Jun 1, 2016 Issued
Array ( [id] => 16879219 [patent_doc_number] => 11029357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Embedded logic analyzer and integrated circuit including the same [patent_app_type] => utility [patent_app_number] => 15/170020 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 12907 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170020 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170020
Embedded logic analyzer and integrated circuit including the same May 31, 2016 Issued
Array ( [id] => 11938604 [patent_doc_number] => 20170242754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/170383 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170383
SEMICONDUCTOR DEVICE May 31, 2016 Abandoned
Array ( [id] => 12986194 [patent_doc_number] => 20170344426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => COMPUTING SYSTEM WITH DATA PROTECTION ENHANCEMENT MECHANISM AND METHOD OF OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 15/169279 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169279
Computing system with data protection enhancement mechanism and method of operation thereof May 30, 2016 Issued
Array ( [id] => 12025765 [patent_doc_number] => 20170315864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT' [patent_app_type] => utility [patent_app_number] => 15/147032 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147032
HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT May 4, 2016 Abandoned
Array ( [id] => 12025764 [patent_doc_number] => 20170315863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT' [patent_app_type] => utility [patent_app_number] => 15/147029 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147029
HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT May 4, 2016 Abandoned
Array ( [id] => 12027592 [patent_doc_number] => 20170317691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT' [patent_app_type] => utility [patent_app_number] => 15/142127 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15142127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/142127
HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT Apr 28, 2016 Abandoned
Array ( [id] => 11990833 [patent_doc_number] => 20170294987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'BROADCAST SIGNAL FRAME GENERATION DEVICE AND BROADCAST SIGNAL FRAME GENERATION METHOD USING BOUNDARY OF PHYSICAL LAYER PIPES OF CORE LAYER' [patent_app_type] => utility [patent_app_number] => 15/532065 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15532065 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/532065
Broadcast signal frame generation device and broadcast signal frame generation method using boundary of physical layer pipes of core layer Mar 24, 2016 Issued
Array ( [id] => 14037267 [patent_doc_number] => 10230397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Construction method for (n,n(n-1),n-1) permutation group code based on coset partition and codebook generator thereof [patent_app_type] => utility [patent_app_number] => 15/060111 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7336 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 940 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060111 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060111
Construction method for (n,n(n-1),n-1) permutation group code based on coset partition and codebook generator thereof Mar 2, 2016 Issued
Array ( [id] => 14527357 [patent_doc_number] => 10340952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Transmitter and shortening method thereof [patent_app_type] => utility [patent_app_number] => 15/058353 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 28970 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058353
Transmitter and shortening method thereof Mar 1, 2016 Issued
Array ( [id] => 16522195 [patent_doc_number] => 10873422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Method for executing HARQ in wireless communication system and device therefor [patent_app_type] => utility [patent_app_number] => 16/079652 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 50 [patent_no_of_words] => 26269 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16079652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/079652
Method for executing HARQ in wireless communication system and device therefor Feb 25, 2016 Issued
Array ( [id] => 13212735 [patent_doc_number] => 10120737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Apparatus for detecting bugs in logic-based processing devices [patent_app_type] => utility [patent_app_number] => 15/047376 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3249 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/047376
Apparatus for detecting bugs in logic-based processing devices Feb 17, 2016 Issued
Array ( [id] => 11044405 [patent_doc_number] => 20160241361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'EMBEDDED SYSTEM AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/044997 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5025 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15044997 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/044997
Embedded system and method thereof Feb 15, 2016 Issued
Array ( [id] => 11044301 [patent_doc_number] => 20160241257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'Decoding Low-Density Parity-Check Maximum-Likelihood Single-Bit Messages' [patent_app_type] => utility [patent_app_number] => 15/042365 [patent_app_country] => US [patent_app_date] => 2016-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4984 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/042365
Decoding low-density parity-check maximum-likelihood single-bit messages Feb 11, 2016 Issued
Array ( [id] => 15169587 [patent_doc_number] => 10490296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Memory built-in self-test (MBIST) test time reduction [patent_app_type] => utility [patent_app_number] => 15/019590 [patent_app_country] => US [patent_app_date] => 2016-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15019590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/019590
Memory built-in self-test (MBIST) test time reduction Feb 8, 2016 Issued
Array ( [id] => 13756299 [patent_doc_number] => 10171108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-01 [patent_title] => Parallel CRC calculation for multiple packets without requiring a shifter [patent_app_type] => utility [patent_app_number] => 15/016672 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016672
Parallel CRC calculation for multiple packets without requiring a shifter Feb 4, 2016 Issued
Array ( [id] => 14829611 [patent_doc_number] => 10411830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Codeword builder for communication systems [patent_app_type] => utility [patent_app_number] => 15/011605 [patent_app_country] => US [patent_app_date] => 2016-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 13564 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011605 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011605
Codeword builder for communication systems Jan 30, 2016 Issued
Array ( [id] => 11397008 [patent_doc_number] => 20170017544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'SYSTEMS AND METHODS FOR PROVIDING LOW LATENCY READ PATH FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/963025 [patent_app_country] => US [patent_app_date] => 2015-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6084 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963025
SYSTEMS AND METHODS FOR PROVIDING LOW LATENCY READ PATH FOR NON-VOLATILE MEMORY Dec 7, 2015 Abandoned
Array ( [id] => 11592602 [patent_doc_number] => 20170117014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'EFFICIENT RECOVERY OF THE CODEWORD INTERLEAVE ADDRESS' [patent_app_type] => utility [patent_app_number] => 14/923389 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10258 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14923389 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/923389
Efficient recovery of the codeword interleave address Oct 25, 2015 Issued
Array ( [id] => 11543563 [patent_doc_number] => 20170097388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'LBIST DEBUG CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/875717 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4316 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875717 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/875717
LBIST debug controller Oct 5, 2015 Issued
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