
Hannah J. Pak
Examiner (ID: 7389, Phone: (571)270-5456 , Office: P/1764 )
| Most Active Art Unit | 1764 |
| Art Unit(s) | 1796, 1764 |
| Total Applications | 1287 |
| Issued Applications | 948 |
| Pending Applications | 88 |
| Abandoned Applications | 275 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5833396
[patent_doc_number] => 20060245226
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Fully buffered DIMM architecture and protocol'
[patent_app_type] => utility
[patent_app_number] => 11/120913
[patent_app_country] => US
[patent_app_date] => 2005-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3393
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20060245226.pdf
[firstpage_image] =>[orig_patent_app_number] => 11120913
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/120913 | Fully buffered DIMM architecture and protocol | May 1, 2005 | Abandoned |
Array
(
[id] => 5836448
[patent_doc_number] => 20060248280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Prefetch address generation implementing multiple confidence levels'
[patent_app_type] => utility
[patent_app_number] => 11/120287
[patent_app_country] => US
[patent_app_date] => 2005-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 11280
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20060248280.pdf
[firstpage_image] =>[orig_patent_app_number] => 11120287
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/120287 | Prefetch address generation implementing multiple confidence levels | May 1, 2005 | Abandoned |
Array
(
[id] => 368250
[patent_doc_number] => 07480773
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-01-20
[patent_title] => 'Virtual machine use and optimization of hardware configurations'
[patent_app_type] => utility
[patent_app_number] => 11/119567
[patent_app_country] => US
[patent_app_date] => 2005-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4786
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/480/07480773.pdf
[firstpage_image] =>[orig_patent_app_number] => 11119567
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/119567 | Virtual machine use and optimization of hardware configurations | May 1, 2005 | Issued |
Array
(
[id] => 5836447
[patent_doc_number] => 20060248279
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Prefetching across a page boundary'
[patent_app_type] => utility
[patent_app_number] => 11/120272
[patent_app_country] => US
[patent_app_date] => 2005-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10979
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20060248279.pdf
[firstpage_image] =>[orig_patent_app_number] => 11120272
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/120272 | Prefetching across a page boundary | May 1, 2005 | Abandoned |
Array
(
[id] => 340208
[patent_doc_number] => 07506105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-17
[patent_title] => 'Prefetching using hashed program counter'
[patent_app_type] => utility
[patent_app_number] => 11/120288
[patent_app_country] => US
[patent_app_date] => 2005-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 11212
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/506/07506105.pdf
[firstpage_image] =>[orig_patent_app_number] => 11120288
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/120288 | Prefetching using hashed program counter | May 1, 2005 | Issued |
Array
(
[id] => 5836555
[patent_doc_number] => 20060248387
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'In-line non volatile memory disk read cache and write buffer'
[patent_app_type] => utility
[patent_app_number] => 11/107551
[patent_app_country] => US
[patent_app_date] => 2005-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8284
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20060248387.pdf
[firstpage_image] =>[orig_patent_app_number] => 11107551
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/107551 | In-line non volatile memory disk read cache and write buffer | Apr 14, 2005 | Issued |
Array
(
[id] => 5036511
[patent_doc_number] => 20070101050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'Flexible formatting for universal storage device'
[patent_app_type] => utility
[patent_app_number] => 10/560682
[patent_app_country] => US
[patent_app_date] => 2004-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6191
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20070101050.pdf
[firstpage_image] =>[orig_patent_app_number] => 10560682
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/560682 | Flexible formatting for universal storage device | Jun 14, 2004 | Issued |
Array
(
[id] => 5592278
[patent_doc_number] => 20060041731
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-23
[patent_title] => 'Method and device for persistent-memory mangement'
[patent_app_type] => utility
[patent_app_number] => 10/533735
[patent_app_country] => US
[patent_app_date] => 2003-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8926
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20060041731.pdf
[firstpage_image] =>[orig_patent_app_number] => 10533735
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/533735 | Method and device for persistent-memory mangement | Oct 12, 2003 | Abandoned |
Array
(
[id] => 7118960
[patent_doc_number] => 20050071707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Integrated circuit with bi-modal data strobe'
[patent_app_type] => utility
[patent_app_number] => 10/676648
[patent_app_country] => US
[patent_app_date] => 2003-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6058
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20050071707.pdf
[firstpage_image] =>[orig_patent_app_number] => 10676648
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676648 | Integrated circuit with bi-modal data strobe | Sep 29, 2003 | Abandoned |