Search

Harold J. Kim

Examiner (ID: 351)

Most Active Art Unit
2182
Art Unit(s)
2732, 2781, 2181, 2182, 2782, 2783
Total Applications
260
Issued Applications
222
Pending Applications
11
Abandoned Applications
27

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4151344 [patent_doc_number] => 06035348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method for managing multiple ordered sets by dequeuing selected data packet from single memory structure' [patent_app_type] => 1 [patent_app_number] => 8/885010 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6006 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035348.pdf [firstpage_image] =>[orig_patent_app_number] => 885010 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885010
Method for managing multiple ordered sets by dequeuing selected data packet from single memory structure Jun 29, 1997 Issued
Array ( [id] => 4158331 [patent_doc_number] => 06031973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Robot and its controller method' [patent_app_type] => 1 [patent_app_number] => 8/876697 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8356 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031973.pdf [firstpage_image] =>[orig_patent_app_number] => 876697 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876697
Robot and its controller method Jun 15, 1997 Issued
Array ( [id] => 4085107 [patent_doc_number] => 06009491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Data transmission method having a data line which is separate from a data bus and is designed as a chain' [patent_app_type] => 1 [patent_app_number] => 8/876404 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2249 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009491.pdf [firstpage_image] =>[orig_patent_app_number] => 876404 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876404
Data transmission method having a data line which is separate from a data bus and is designed as a chain Jun 15, 1997 Issued
Array ( [id] => 3957451 [patent_doc_number] => 05974239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Data transfer method for a bus device in a computer system by placing first and second addresses corresponding to a bridge and with the bus device respectively on a bus' [patent_app_type] => 1 [patent_app_number] => 8/873213 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5160 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974239.pdf [firstpage_image] =>[orig_patent_app_number] => 873213 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873213
Data transfer method for a bus device in a computer system by placing first and second addresses corresponding to a bridge and with the bus device respectively on a bus Jun 10, 1997 Issued
Array ( [id] => 3915857 [patent_doc_number] => 05951657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Cacheable interface control registers for high speed data transfer' [patent_app_type] => 1 [patent_app_number] => 8/871145 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5968 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951657.pdf [firstpage_image] =>[orig_patent_app_number] => 871145 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871145
Cacheable interface control registers for high speed data transfer Jun 8, 1997 Issued
Array ( [id] => 4030330 [patent_doc_number] => 05907712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Method for reducing processor interrupt processing time by transferring predetermined interrupt status to a system memory for eliminating PIO reads from the interrupt handler' [patent_app_type] => 1 [patent_app_number] => 8/865822 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2291 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907712.pdf [firstpage_image] =>[orig_patent_app_number] => 865822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865822
Method for reducing processor interrupt processing time by transferring predetermined interrupt status to a system memory for eliminating PIO reads from the interrupt handler May 29, 1997 Issued
Array ( [id] => 4036622 [patent_doc_number] => 05968146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Data transfer device for decreasing load of CPU by avoiding direct control from the CPU in parallel computer system' [patent_app_type] => 1 [patent_app_number] => 8/864692 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6416 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968146.pdf [firstpage_image] =>[orig_patent_app_number] => 864692 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864692
Data transfer device for decreasing load of CPU by avoiding direct control from the CPU in parallel computer system May 27, 1997 Issued
Array ( [id] => 4148972 [patent_doc_number] => 06016549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Peripheral unit having at least two sequencer circuits configured to control data transfers for power saving' [patent_app_type] => 1 [patent_app_number] => 8/863898 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6309 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016549.pdf [firstpage_image] =>[orig_patent_app_number] => 863898 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863898
Peripheral unit having at least two sequencer circuits configured to control data transfers for power saving May 26, 1997 Issued
Array ( [id] => 4003093 [patent_doc_number] => 05960208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Data communication adapter for selectively supplying power to a communication control circuit or a portable terminal unit' [patent_app_type] => 1 [patent_app_number] => 8/862450 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 33 [patent_no_of_words] => 11891 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960208.pdf [firstpage_image] =>[orig_patent_app_number] => 862450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862450
Data communication adapter for selectively supplying power to a communication control circuit or a portable terminal unit May 22, 1997 Issued
Array ( [id] => 3966756 [patent_doc_number] => 05983290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Information processing system using portable terminal unit and data communication adapter therefor' [patent_app_type] => 1 [patent_app_number] => 8/862700 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 33 [patent_no_of_words] => 11890 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983290.pdf [firstpage_image] =>[orig_patent_app_number] => 862700 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862700
Information processing system using portable terminal unit and data communication adapter therefor May 22, 1997 Issued
Array ( [id] => 3936017 [patent_doc_number] => 05915120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Information processing apparatus having a power management system that dynamically changes operating conditions based upon dynamically selected user preferential order setting' [patent_app_type] => 1 [patent_app_number] => 8/855447 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 11107 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915120.pdf [firstpage_image] =>[orig_patent_app_number] => 855447 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855447
Information processing apparatus having a power management system that dynamically changes operating conditions based upon dynamically selected user preferential order setting May 12, 1997 Issued
Array ( [id] => 4023373 [patent_doc_number] => 05889970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Dual purpose apparatus, method and system for accelerated graphics port and peripheral component interconnect' [patent_app_type] => 1 [patent_app_number] => 8/853289 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7830 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889970.pdf [firstpage_image] =>[orig_patent_app_number] => 853289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853289
Dual purpose apparatus, method and system for accelerated graphics port and peripheral component interconnect May 8, 1997 Issued
Array ( [id] => 3967001 [patent_doc_number] => 05916312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members' [patent_app_type] => 1 [patent_app_number] => 8/851695 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8566 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/916/05916312.pdf [firstpage_image] =>[orig_patent_app_number] => 851695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851695
ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members May 5, 1997 Issued
Array ( [id] => 3996319 [patent_doc_number] => 05911081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Method and apparatus for selectively inhibiting power shutdowns based upon the number of power shutdowns that an electrical device has been experienced' [patent_app_type] => 1 [patent_app_number] => 8/851308 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2725 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911081.pdf [firstpage_image] =>[orig_patent_app_number] => 851308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851308
Method and apparatus for selectively inhibiting power shutdowns based upon the number of power shutdowns that an electrical device has been experienced May 4, 1997 Issued
Array ( [id] => 4081291 [patent_doc_number] => 05867670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Self-control type bus arbitration circuit and arbitration method therefor' [patent_app_type] => 1 [patent_app_number] => 8/851439 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3832 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867670.pdf [firstpage_image] =>[orig_patent_app_number] => 851439 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851439
Self-control type bus arbitration circuit and arbitration method therefor May 4, 1997 Issued
Array ( [id] => 4215411 [patent_doc_number] => 06014720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Dynamically sizing a bus transaction for dual bus size interoperability based on bus transaction signals' [patent_app_type] => 1 [patent_app_number] => 8/851352 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 7583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014720.pdf [firstpage_image] =>[orig_patent_app_number] => 851352 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851352
Dynamically sizing a bus transaction for dual bus size interoperability based on bus transaction signals May 4, 1997 Issued
Array ( [id] => 4014545 [patent_doc_number] => 05923858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method and apparatus to interface a peripheral device operating in an internal clock domain to a PCI bus operating in a PCI clock domain' [patent_app_type] => 1 [patent_app_number] => 8/850121 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6072 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923858.pdf [firstpage_image] =>[orig_patent_app_number] => 850121 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850121
Method and apparatus to interface a peripheral device operating in an internal clock domain to a PCI bus operating in a PCI clock domain Apr 30, 1997 Issued
Array ( [id] => 3969239 [patent_doc_number] => 05948105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method for conserving power by adjusting clock frequency based on a repetitive timing cycle' [patent_app_type] => 1 [patent_app_number] => 8/834434 [patent_app_country] => US [patent_app_date] => 1997-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11069 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948105.pdf [firstpage_image] =>[orig_patent_app_number] => 834434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834434
Method for conserving power by adjusting clock frequency based on a repetitive timing cycle Apr 15, 1997 Issued
Array ( [id] => 4042297 [patent_doc_number] => 05931924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights' [patent_app_type] => 1 [patent_app_number] => 8/839437 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3527 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931924.pdf [firstpage_image] =>[orig_patent_app_number] => 839437 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839437
Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights Apr 13, 1997 Issued
Array ( [id] => 4026005 [patent_doc_number] => 05941968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device' [patent_app_type] => 1 [patent_app_number] => 8/837120 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6157 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941968.pdf [firstpage_image] =>[orig_patent_app_number] => 837120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837120
Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device Apr 13, 1997 Issued
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