Search

Harold J. Kim

Examiner (ID: 16903)

Most Active Art Unit
2182
Art Unit(s)
2181, 2781, 2782, 2182, 2783, 2732
Total Applications
260
Issued Applications
222
Pending Applications
11
Abandoned Applications
27

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1602167 [patent_doc_number] => 06493772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'System and method with guaranteed maximum command response time' [patent_app_type] => B1 [patent_app_number] => 09/379542 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7035 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493772.pdf [firstpage_image] =>[orig_patent_app_number] => 09379542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/379542
System and method with guaranteed maximum command response time Aug 22, 1999 Issued
Array ( [id] => 1423300 [patent_doc_number] => 06539439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method and apparatus for interfacing a bus at an independent rate with input/output devices' [patent_app_type] => B1 [patent_app_number] => 09/376874 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6057 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539439.pdf [firstpage_image] =>[orig_patent_app_number] => 09376874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376874
Method and apparatus for interfacing a bus at an independent rate with input/output devices Aug 17, 1999 Issued
Array ( [id] => 7644161 [patent_doc_number] => 06473813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Module based address translation arrangement and transaction offloading in a digital system' [patent_app_type] => B1 [patent_app_number] => 09/376763 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2884 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473813.pdf [firstpage_image] =>[orig_patent_app_number] => 09376763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376763
Module based address translation arrangement and transaction offloading in a digital system Aug 16, 1999 Issued
Array ( [id] => 1348466 [patent_doc_number] => 06598175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Operating system shutdown absent a display and keyboard for a processor located on a printed circuit board' [patent_app_type] => B1 [patent_app_number] => 09/365194 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2062 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598175.pdf [firstpage_image] =>[orig_patent_app_number] => 09365194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365194
Operating system shutdown absent a display and keyboard for a processor located on a printed circuit board Aug 1, 1999 Issued
Array ( [id] => 1423871 [patent_doc_number] => 06539492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'System and method for maintaining synchronization in a computer storage system' [patent_app_type] => B1 [patent_app_number] => 09/365375 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7913 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539492.pdf [firstpage_image] =>[orig_patent_app_number] => 09365375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365375
System and method for maintaining synchronization in a computer storage system Jul 29, 1999 Issued
Array ( [id] => 1366086 [patent_doc_number] => 06584517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Circuit and method for supporting multicast/broadcast operations in multi-queue storage devices' [patent_app_type] => B1 [patent_app_number] => 09/347046 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3484 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584517.pdf [firstpage_image] =>[orig_patent_app_number] => 09347046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347046
Circuit and method for supporting multicast/broadcast operations in multi-queue storage devices Jul 1, 1999 Issued
Array ( [id] => 7644108 [patent_doc_number] => 06473866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Time synchronizing method for switching system' [patent_app_type] => B1 [patent_app_number] => 09/342910 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6657 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473866.pdf [firstpage_image] =>[orig_patent_app_number] => 09342910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342910
Time synchronizing method for switching system Jun 29, 1999 Issued
Array ( [id] => 6736945 [patent_doc_number] => 20030014580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'A SCSI PHASE STATUS REGISTER FOR USE IN REDUCING INSTRUCTIONS EXECUTED BY AN ON-CHIP SEQUENCER IN ASSERTING A SCSI ACKOWLEDGE SIGNAL AND METHOD' [patent_app_type] => new [patent_app_number] => 09/343324 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4242 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014580.pdf [firstpage_image] =>[orig_patent_app_number] => 09343324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343324
SCSI phase status register for use in reducing instructions executed by an on-chip sequencer in asserting a SCSI acknowledge signal and method Jun 29, 1999 Issued
Array ( [id] => 1573698 [patent_doc_number] => 06499070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Circuitry and method of transferring parallel and serial data' [patent_app_type] => B1 [patent_app_number] => 09/326292 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3697 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499070.pdf [firstpage_image] =>[orig_patent_app_number] => 09326292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326292
Circuitry and method of transferring parallel and serial data Jun 6, 1999 Issued
Array ( [id] => 1068384 [patent_doc_number] => 06848058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-25 [patent_title] => 'Power reduction circuit and method with multi clock branch control' [patent_app_type] => utility [patent_app_number] => 09/325882 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4194 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848058.pdf [firstpage_image] =>[orig_patent_app_number] => 09325882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325882
Power reduction circuit and method with multi clock branch control Jun 3, 1999 Issued
Array ( [id] => 1572214 [patent_doc_number] => 06378011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Parallel to serial asynchronous hardware assisted DSP interface' [patent_app_type] => B1 [patent_app_number] => 09/322744 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4585 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378011.pdf [firstpage_image] =>[orig_patent_app_number] => 09322744 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322744
Parallel to serial asynchronous hardware assisted DSP interface May 27, 1999 Issued
Array ( [id] => 1431954 [patent_doc_number] => 06516422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Computer system including multiple clock sources and failover switching' [patent_app_type] => B1 [patent_app_number] => 09/320794 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5878 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516422.pdf [firstpage_image] =>[orig_patent_app_number] => 09320794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320794
Computer system including multiple clock sources and failover switching May 26, 1999 Issued
Array ( [id] => 1452210 [patent_doc_number] => 06370600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency' [patent_app_type] => B1 [patent_app_number] => 09/320127 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9202 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370600.pdf [firstpage_image] =>[orig_patent_app_number] => 09320127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320127
Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency May 24, 1999 Issued
Array ( [id] => 1456621 [patent_doc_number] => 06457070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Apparatus and method for identifying location of a peripheral unit in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/297799 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457070.pdf [firstpage_image] =>[orig_patent_app_number] => 09297799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/297799
Apparatus and method for identifying location of a peripheral unit in a computer system May 5, 1999 Issued
Array ( [id] => 4203790 [patent_doc_number] => 06151646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'System for resources under control of docking station when stand alone and resources under control of central processing unit of portable computer when docked' [patent_app_type] => 1 [patent_app_number] => 9/304935 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 328 [patent_figures_cnt] => 427 [patent_no_of_words] => 62570 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151646.pdf [firstpage_image] =>[orig_patent_app_number] => 304935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304935
System for resources under control of docking station when stand alone and resources under control of central processing unit of portable computer when docked May 3, 1999 Issued
Array ( [id] => 1296925 [patent_doc_number] => 06633929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method and system for abstracting network device drivers' [patent_app_type] => B1 [patent_app_number] => 09/302735 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6842 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633929.pdf [firstpage_image] =>[orig_patent_app_number] => 09302735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302735
Method and system for abstracting network device drivers Apr 29, 1999 Issued
Array ( [id] => 1116523 [patent_doc_number] => 06804724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Analog/digital display adapter and a computer system having the same' [patent_app_type] => B2 [patent_app_number] => 09/301609 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 6105 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804724.pdf [firstpage_image] =>[orig_patent_app_number] => 09301609 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301609
Analog/digital display adapter and a computer system having the same Apr 28, 1999 Issued
09/297170 PERSONALIZED AUTOMATED OPERATOR POSITION Apr 26, 1999 Abandoned
Array ( [id] => 6460175 [patent_doc_number] => 20020178306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'METHOD AND SYSTEM FOR OVER-RUN PROTECTION IN AMESSAGE PASSING MULTI-PROCESSOR COMPUTER SYSTEM USING A CREDIT-BASED PROTOCOL' [patent_app_type] => new [patent_app_number] => 09/287650 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3174 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178306.pdf [firstpage_image] =>[orig_patent_app_number] => 09287650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287650
Method and system for over-run protection in a message passing multi-processor computer system using a credit-based protocol Apr 6, 1999 Issued
Array ( [id] => 4088339 [patent_doc_number] => 06070203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS' [patent_app_type] => 1 [patent_app_number] => 9/201413 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4093 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070203.pdf [firstpage_image] =>[orig_patent_app_number] => 201413 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/201413
Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS Nov 29, 1998 Issued
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