Search

Harold Joyce

Examiner (ID: 11998)

Most Active Art Unit
3404
Art Unit(s)
3502, 3404, 3749, 3744, 2899
Total Applications
2782
Issued Applications
2512
Pending Applications
61
Abandoned Applications
209

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20616499 [patent_doc_number] => 20260086592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => TEMPERATURE DRIFT COMPENSATION FOR GENERATING A REFERENCE VOLTAGE [patent_app_type] => utility [patent_app_number] => 19/066930 [patent_app_country] => US [patent_app_date] => 2025-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19066930 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/066930
TEMPERATURE DRIFT COMPENSATION FOR GENERATING A REFERENCE VOLTAGE Feb 27, 2025 Pending
Array ( [id] => 20089698 [patent_doc_number] => 20250219634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SIGNAL TRANSMITTING APPARATUS [patent_app_type] => utility [patent_app_number] => 19/063813 [patent_app_country] => US [patent_app_date] => 2025-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19063813 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/063813
SIGNAL TRANSMITTING APPARATUS Feb 25, 2025 Pending
Array ( [id] => 20461956 [patent_doc_number] => 20260011385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => SHIFT REGISTERS [patent_app_type] => utility [patent_app_number] => 19/062533 [patent_app_country] => US [patent_app_date] => 2025-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19062533 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/062533
SHIFT REGISTERS Feb 24, 2025 Pending
Array ( [id] => 20223611 [patent_doc_number] => 20250286542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS INCLUDING THE SAME, AND BUS SYSTEM [patent_app_type] => utility [patent_app_number] => 19/037760 [patent_app_country] => US [patent_app_date] => 2025-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19037760 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/037760
SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS INCLUDING THE SAME, AND BUS SYSTEM Jan 26, 2025 Pending
Array ( [id] => 20017693 [patent_doc_number] => 20250155915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => INTERFACE SYSTEM [patent_app_type] => utility [patent_app_number] => 19/022165 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022165 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/022165
INTERFACE SYSTEM Jan 14, 2025 Pending
Array ( [id] => 20020378 [patent_doc_number] => 20250158600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => DYNAMIC D FLIP-FLOP, DATA OPERATION UNIT, CHIP, HASH BOARD AND COMPUTING DEVICE [patent_app_type] => utility [patent_app_number] => 19/020207 [patent_app_country] => US [patent_app_date] => 2025-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19020207 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/020207
DYNAMIC D FLIP-FLOP, DATA OPERATION UNIT, CHIP, HASH BOARD AND COMPUTING DEVICE Jan 13, 2025 Pending
Array ( [id] => 20011845 [patent_doc_number] => 20250150067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => FREQUENCY SELECTIVE LIMITER HAVING REDUCED SPIKE LEAKAGE [patent_app_type] => utility [patent_app_number] => 19/016287 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19016287 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/016287
FREQUENCY SELECTIVE LIMITER HAVING REDUCED SPIKE LEAKAGE Jan 9, 2025 Pending
Array ( [id] => 19987574 [patent_doc_number] => 20250125796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => LOW-JITTER RANDOM CLOCK GENERATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 19/002656 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002656 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/002656
LOW-JITTER RANDOM CLOCK GENERATION CIRCUIT Dec 25, 2024 Pending
Array ( [id] => 20182879 [patent_doc_number] => 20250266837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SWITCHING CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 19/002299 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002299 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/002299
SWITCHING CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE Dec 25, 2024 Pending
Array ( [id] => 20054542 [patent_doc_number] => 20250192764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DIGITAL PHASE INTERPOLATOR [patent_app_type] => utility [patent_app_number] => 18/968228 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18968228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/968228
DIGITAL PHASE INTERPOLATOR Dec 3, 2024 Pending
Array ( [id] => 20045663 [patent_doc_number] => 20250183885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => PROGRAMMABLE GATE DRIVER CIRCUIT FOR AN INTEGRATED POWER SWITCH [patent_app_type] => utility [patent_app_number] => 18/960246 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960246
PROGRAMMABLE GATE DRIVER CIRCUIT FOR AN INTEGRATED POWER SWITCH Nov 25, 2024 Pending
Array ( [id] => 19835797 [patent_doc_number] => 20250087583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => FAIL-OPEN ISOLATOR [patent_app_type] => utility [patent_app_number] => 18/958537 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958537
FAIL-OPEN ISOLATOR Nov 24, 2024 Pending
Array ( [id] => 19821696 [patent_doc_number] => 20250079903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => WIRELESS POWER TRANSMISSION DEVICE [patent_app_type] => utility [patent_app_number] => 18/953586 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18953586 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/953586
Wireless power transmission device Nov 19, 2024 Issued
Array ( [id] => 19804843 [patent_doc_number] => 20250070768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => Controlling Duty Cycle Distortion [patent_app_type] => utility [patent_app_number] => 18/938128 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938128
Controlling Duty Cycle Distortion Nov 4, 2024 Pending
Array ( [id] => 19789089 [patent_doc_number] => 20250062768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => VOLTAGE DROOP MONITOR AND VOLTAGE DROOP MONITORING METHOD [patent_app_type] => utility [patent_app_number] => 18/938263 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938263
VOLTAGE DROOP MONITOR AND VOLTAGE DROOP MONITORING METHOD Nov 4, 2024 Pending
Array ( [id] => 20733474 [patent_doc_number] => 12640736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Input/output circuit with slew rate control [patent_app_type] => utility [patent_app_number] => 18/931163 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18931163 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/931163
Input/output circuit with slew rate control Oct 29, 2024 Issued
Array ( [id] => 20011863 [patent_doc_number] => 20250150085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SYNCHRONOUS TRANSMISSION METHOD, AND CHIP AND SERIAL COMMUNICATION SYSTEM APPLYING THE SAME [patent_app_type] => utility [patent_app_number] => 18/926400 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926400 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926400
SYNCHRONOUS TRANSMISSION METHOD, AND CHIP AND SERIAL COMMUNICATION SYSTEM APPLYING THE SAME Oct 24, 2024 Pending
Array ( [id] => 20544999 [patent_doc_number] => 20260051892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-19 [patent_title] => IMPLEMENTING A LOW POWER TOPOLOGY IN A CLOCKED LATCH [patent_app_type] => utility [patent_app_number] => 18/802876 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/802876
IMPLEMENTING A LOW POWER TOPOLOGY IN A CLOCKED LATCH Aug 12, 2024 Pending
Array ( [id] => 19604896 [patent_doc_number] => 20240395776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 18/790261 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790261 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790261
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE Jul 30, 2024 Pending
Array ( [id] => 20733455 [patent_doc_number] => 12640717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Time interleaving circuit having glitch mitigation [patent_app_type] => utility [patent_app_number] => 18/775622 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775622
Time interleaving circuit having glitch mitigation Jul 16, 2024 Issued
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