Search

Harry B. Tanner

Examiner (ID: 14945)

Most Active Art Unit
3404
Art Unit(s)
3727, 3404, 3744, 2899
Total Applications
2362
Issued Applications
2125
Pending Applications
54
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4148288 [patent_doc_number] => 06128756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'System for optimizing the testing and repair time of a defective integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/150289 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2795 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128756.pdf [firstpage_image] =>[orig_patent_app_number] => 150289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150289
System for optimizing the testing and repair time of a defective integrated circuit Sep 8, 1998 Issued
Array ( [id] => 4162993 [patent_doc_number] => 06032275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Test pattern generator' [patent_app_type] => 1 [patent_app_number] => 9/143902 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2214 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032275.pdf [firstpage_image] =>[orig_patent_app_number] => 143902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143902
Test pattern generator Aug 30, 1998 Issued
Array ( [id] => 4064173 [patent_doc_number] => 05964894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'IC test equipment, measurement method in the IC test equipment, and storage medium of the same' [patent_app_type] => 1 [patent_app_number] => 9/141991 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3684 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964894.pdf [firstpage_image] =>[orig_patent_app_number] => 141991 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141991
IC test equipment, measurement method in the IC test equipment, and storage medium of the same Aug 27, 1998 Issued
Array ( [id] => 4156715 [patent_doc_number] => 06122761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'IC chip tester using compressed digital test data and a method for testing IC chip using the tester' [patent_app_type] => 1 [patent_app_number] => 9/140448 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4061 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122761.pdf [firstpage_image] =>[orig_patent_app_number] => 140448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140448
IC chip tester using compressed digital test data and a method for testing IC chip using the tester Aug 25, 1998 Issued
Array ( [id] => 4022988 [patent_doc_number] => 05987636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Static test sequence compaction using two-phase restoration and segment manipulation' [patent_app_type] => 1 [patent_app_number] => 9/135561 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5554 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987636.pdf [firstpage_image] =>[orig_patent_app_number] => 135561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135561
Static test sequence compaction using two-phase restoration and segment manipulation Aug 17, 1998 Issued
Array ( [id] => 4161245 [patent_doc_number] => 06061813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Memory test set' [patent_app_type] => 1 [patent_app_number] => 9/125312 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4256 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061813.pdf [firstpage_image] =>[orig_patent_app_number] => 125312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/125312
Memory test set Aug 12, 1998 Issued
Array ( [id] => 4202828 [patent_doc_number] => 06094735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Speed-signaling testing for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/128041 [patent_app_country] => US [patent_app_date] => 1998-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2072 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094735.pdf [firstpage_image] =>[orig_patent_app_number] => 128041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128041
Speed-signaling testing for integrated circuits Aug 2, 1998 Issued
Array ( [id] => 4255767 [patent_doc_number] => 06119251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Self-test of a memory device' [patent_app_type] => 1 [patent_app_number] => 9/127043 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8241 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119251.pdf [firstpage_image] =>[orig_patent_app_number] => 127043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127043
Self-test of a memory device Jul 30, 1998 Issued
Array ( [id] => 4085954 [patent_doc_number] => 06009546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Algorithmic pattern generator' [patent_app_type] => 1 [patent_app_number] => 9/126691 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8920 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009546.pdf [firstpage_image] =>[orig_patent_app_number] => 126691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/126691
Algorithmic pattern generator Jul 29, 1998 Issued
Array ( [id] => 4116870 [patent_doc_number] => 06067652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Tester-compatible timing translation system and method using time-set partnering' [patent_app_type] => 1 [patent_app_number] => 9/124494 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4556 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067652.pdf [firstpage_image] =>[orig_patent_app_number] => 124494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124494
Tester-compatible timing translation system and method using time-set partnering Jul 28, 1998 Issued
Array ( [id] => 4202871 [patent_doc_number] => 06094738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Test pattern generation apparatus and method for SDRAM' [patent_app_type] => 1 [patent_app_number] => 9/121954 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3400 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094738.pdf [firstpage_image] =>[orig_patent_app_number] => 121954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/121954
Test pattern generation apparatus and method for SDRAM Jul 23, 1998 Issued
Array ( [id] => 4149155 [patent_doc_number] => 06016561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Output data compression scheme for use in testing IC memories' [patent_app_type] => 1 [patent_app_number] => 9/099831 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7990 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016561.pdf [firstpage_image] =>[orig_patent_app_number] => 099831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099831
Output data compression scheme for use in testing IC memories Jun 17, 1998 Issued
Array ( [id] => 4148302 [patent_doc_number] => 06128757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Low voltage screen for improving the fault coverage of integrated circuit production test programs' [patent_app_type] => 1 [patent_app_number] => 9/098172 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3878 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128757.pdf [firstpage_image] =>[orig_patent_app_number] => 098172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098172
Low voltage screen for improving the fault coverage of integrated circuit production test programs Jun 15, 1998 Issued
Array ( [id] => 4239842 [patent_doc_number] => 06088823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/096860 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4998 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088823.pdf [firstpage_image] =>[orig_patent_app_number] => 096860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096860
Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit Jun 11, 1998 Issued
Array ( [id] => 4133670 [patent_doc_number] => 06047393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Memory testing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/094533 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8424 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047393.pdf [firstpage_image] =>[orig_patent_app_number] => 094533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094533
Memory testing apparatus Jun 11, 1998 Issued
Array ( [id] => 4167888 [patent_doc_number] => 06065142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'ROM testing circuit' [patent_app_type] => 1 [patent_app_number] => 9/096933 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3189 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065142.pdf [firstpage_image] =>[orig_patent_app_number] => 096933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096933
ROM testing circuit Jun 11, 1998 Issued
Array ( [id] => 4239774 [patent_doc_number] => 06088820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Static semiconductor memory device having test mode' [patent_app_type] => 1 [patent_app_number] => 9/094452 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 5032 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088820.pdf [firstpage_image] =>[orig_patent_app_number] => 094452 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094452
Static semiconductor memory device having test mode Jun 9, 1998 Issued
Array ( [id] => 4110870 [patent_doc_number] => 06134686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Technique to detect drive strength of input pin' [patent_app_type] => 1 [patent_app_number] => 9/086870 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2001 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134686.pdf [firstpage_image] =>[orig_patent_app_number] => 086870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086870
Technique to detect drive strength of input pin May 28, 1998 Issued
Array ( [id] => 4260897 [patent_doc_number] => 06092224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Logic analyzer probe assembly with probe and interface boards' [patent_app_type] => 1 [patent_app_number] => 9/086002 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4870 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092224.pdf [firstpage_image] =>[orig_patent_app_number] => 086002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086002
Logic analyzer probe assembly with probe and interface boards May 26, 1998 Issued
Array ( [id] => 4139517 [patent_doc_number] => 06073261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Circuit for evaluating signal timing' [patent_app_type] => 1 [patent_app_number] => 9/083311 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5712 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073261.pdf [firstpage_image] =>[orig_patent_app_number] => 083311 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083311
Circuit for evaluating signal timing May 21, 1998 Issued
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