
Harry B. Tanner
Examiner (ID: 14945)
| Most Active Art Unit | 3404 |
| Art Unit(s) | 3727, 3404, 3744, 2899 |
| Total Applications | 2362 |
| Issued Applications | 2125 |
| Pending Applications | 54 |
| Abandoned Applications | 183 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4148288
[patent_doc_number] => 06128756
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[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'System for optimizing the testing and repair time of a defective integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/150289
[patent_app_country] => US
[patent_app_date] => 1998-09-09
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[pdf_file] => patents/06/128/06128756.pdf
[firstpage_image] =>[orig_patent_app_number] => 150289
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Test pattern generator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143902 | Test pattern generator | Aug 30, 1998 | Issued |
Array
(
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[patent_issue_date] => 1999-10-12
[patent_title] => 'IC test equipment, measurement method in the IC test equipment, and storage medium of the same'
[patent_app_type] => 1
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[patent_app_date] => 1998-08-28
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'IC chip tester using compressed digital test data and a method for testing IC chip using the tester'
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[patent_app_number] => 9/140448
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140448 | IC chip tester using compressed digital test data and a method for testing IC chip using the tester | Aug 25, 1998 | Issued |
Array
(
[id] => 4022988
[patent_doc_number] => 05987636
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[patent_issue_date] => 1999-11-16
[patent_title] => 'Static test sequence compaction using two-phase restoration and segment manipulation'
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Array
(
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[patent_issue_date] => 2000-05-09
[patent_title] => 'Memory test set'
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Array
(
[id] => 4202828
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Array
(
[id] => 4255767
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[patent_title] => 'Self-test of a memory device'
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[pdf_file] => patents/06/119/06119251.pdf
[firstpage_image] =>[orig_patent_app_number] => 127043
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/127043 | Self-test of a memory device | Jul 30, 1998 | Issued |
Array
(
[id] => 4085954
[patent_doc_number] => 06009546
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[patent_issue_date] => 1999-12-28
[patent_title] => 'Algorithmic pattern generator'
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Array
(
[id] => 4116870
[patent_doc_number] => 06067652
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[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Tester-compatible timing translation system and method using time-set partnering'
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Array
(
[id] => 4202871
[patent_doc_number] => 06094738
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[patent_issue_date] => 2000-07-25
[patent_title] => 'Test pattern generation apparatus and method for SDRAM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121954 | Test pattern generation apparatus and method for SDRAM | Jul 23, 1998 | Issued |
Array
(
[id] => 4149155
[patent_doc_number] => 06016561
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Array
(
[id] => 4148302
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/094452 | Static semiconductor memory device having test mode | Jun 9, 1998 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/083311 | Circuit for evaluating signal timing | May 21, 1998 | Issued |