Search

Harry Chong Hyun Kim

Examiner (ID: 5257)

Art Unit(s)
3509, 3626, 3501, 3629, IPLA, 3902
Total Applications
3029
Issued Applications
800
Pending Applications
1737
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20470979 [patent_doc_number] => 12527025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Semiconductor device with doped region between gate and drain [patent_app_type] => utility [patent_app_number] => 18/625798 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 3289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625798
Semiconductor device with doped region between gate and drain Apr 2, 2024 Issued
Array ( [id] => 19561844 [patent_doc_number] => 20240373636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MICROELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/621738 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621738
METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MICROELECTRONIC DEVICES Mar 28, 2024 Pending
Array ( [id] => 19305775 [patent_doc_number] => 20240234355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => MODULE [patent_app_type] => utility [patent_app_number] => 18/614965 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614965 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614965
MODULE Mar 24, 2024 Pending
Array ( [id] => 19269658 [patent_doc_number] => 20240213363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR DEVICE AND METHOD OF FABRICATION [patent_app_type] => utility [patent_app_number] => 18/596271 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596271 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596271
Vertical field effect transistor device and method of fabrication Mar 4, 2024 Issued
Array ( [id] => 19237549 [patent_doc_number] => 20240194744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SHIELDING STRUCTURE FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/421158 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421158
SHIELDING STRUCTURE FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES Feb 27, 2024 Pending
Array ( [id] => 20457441 [patent_doc_number] => 12520513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Regrowth uniformity in GaN vertical devices [patent_app_type] => utility [patent_app_number] => 18/587327 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 3920 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587327
Regrowth uniformity in GaN vertical devices Feb 25, 2024 Issued
Array ( [id] => 19604865 [patent_doc_number] => 20240395745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/433177 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433177
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME Feb 4, 2024 Pending
Array ( [id] => 19206364 [patent_doc_number] => 20240178263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => DUAL FACING BSI IMAGE SENSORS WITH WAFER LEVEL STACKING [patent_app_type] => utility [patent_app_number] => 18/433120 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433120
DUAL FACING BSI IMAGE SENSORS WITH WAFER LEVEL STACKING Feb 4, 2024 Pending
Array ( [id] => 19206392 [patent_doc_number] => 20240178291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => TRANSISTOR UNIT INCLUDING SHARED GATE STRUCTURE, AND SUB-WORD LINE DRIVER AND SEMICONDUCTOR DEVICE BASED ON THE SAME TRANSISTOR UNIT [patent_app_type] => utility [patent_app_number] => 18/431628 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431628
TRANSISTOR UNIT INCLUDING SHARED GATE STRUCTURE, AND SUB-WORD LINE DRIVER AND SEMICONDUCTOR DEVICE BASED ON THE SAME TRANSISTOR UNIT Feb 1, 2024 Pending
Array ( [id] => 19835774 [patent_doc_number] => 20250087560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => STRUCTURES AND METHODS TO MAXIMIZE CONTACT DENSITY ACROSS CAVITIES [patent_app_type] => utility [patent_app_number] => 18/428390 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428390
STRUCTURES AND METHODS TO MAXIMIZE CONTACT DENSITY ACROSS CAVITIES Jan 30, 2024 Pending
Array ( [id] => 20139519 [patent_doc_number] => 20250246563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => PARTIALLY PULSE-PLATED BOND PADS [patent_app_type] => utility [patent_app_number] => 18/428472 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428472
PARTIALLY PULSE-PLATED BOND PADS Jan 30, 2024 Pending
Array ( [id] => 19662137 [patent_doc_number] => 20240429202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/417004 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417004 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417004
SEMICONDUCTOR PACKAGE Jan 18, 2024 Pending
Array ( [id] => 19286027 [patent_doc_number] => 20240222505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DESIGNS FOR SILICON CARBIDE MOSFETs [patent_app_type] => utility [patent_app_number] => 18/412650 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412650 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412650
DESIGNS FOR SILICON CARBIDE MOSFETs Jan 14, 2024 Abandoned
Array ( [id] => 19390996 [patent_doc_number] => 20240280866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/409804 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409804
ELECTRONIC DEVICE Jan 10, 2024 Pending
Array ( [id] => 19146517 [patent_doc_number] => 20240145547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application [patent_app_type] => utility [patent_app_number] => 18/409045 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409045
MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application Jan 9, 2024 Pending
Array ( [id] => 19366112 [patent_doc_number] => 20240268146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/406397 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406397
METHOD OF MANUFACTURING DISPLAY DEVICE Jan 7, 2024 Pending
Array ( [id] => 19468135 [patent_doc_number] => 20240321805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => WET ATOMIC LAYER ETCHING METHOD AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/405791 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/405791
WET ATOMIC LAYER ETCHING METHOD AND METHOD OF MANUFACTURING THE SAME Jan 4, 2024 Pending
Array ( [id] => 20072316 [patent_doc_number] => 20250210538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => APPARATUS, SYSTEM, AND METHOD FOR UNIQUELY IDENTIFYING INDIVIDUAL DIES ACROSS DIE STACKS [patent_app_type] => utility [patent_app_number] => 18/395203 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395203
APPARATUS, SYSTEM, AND METHOD FOR UNIQUELY IDENTIFYING INDIVIDUAL DIES ACROSS DIE STACKS Dec 21, 2023 Pending
Array ( [id] => 19255148 [patent_doc_number] => 20240206145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Stacked SRAM Cell with a Dual-Side Interconnect Structure [patent_app_type] => utility [patent_app_number] => 18/545760 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545760
Stacked SRAM Cell with a Dual-Side Interconnect Structure Dec 18, 2023 Pending
Array ( [id] => 20063440 [patent_doc_number] => 20250201662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => INTEGRATED CIRCUIT DEVICE INCLUDING THERMAL INTERPOSER LAYER [patent_app_type] => utility [patent_app_number] => 18/538738 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538738
INTEGRATED CIRCUIT DEVICE INCLUDING THERMAL INTERPOSER LAYER Dec 12, 2023 Pending
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