Search

Harry Raymond Behm

Examiner (ID: 474, Phone: (571)272-8929 , Office: P/2838 )

Most Active Art Unit
2838
Art Unit(s)
2838, 2839
Total Applications
1485
Issued Applications
1125
Pending Applications
96
Abandoned Applications
280

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20641098 [patent_doc_number] => 20260099454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-09 [patent_title] => OPTICAL MEMORY MODULE, CACHE MANAGER FOR AN OPTICAL MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 19/417306 [patent_app_country] => US [patent_app_date] => 2025-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19417306 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/417306
OPTICAL MEMORY MODULE, CACHE MANAGER FOR AN OPTICAL MEMORY MODULE Dec 10, 2025 Pending
Array ( [id] => 20281943 [patent_doc_number] => 20250307185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Semiconductor Device and Communication System [patent_app_type] => utility [patent_app_number] => 19/093248 [patent_app_country] => US [patent_app_date] => 2025-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19093248 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/093248
Semiconductor Device and Communication System Mar 26, 2025 Pending
Array ( [id] => 20089931 [patent_doc_number] => 20250219867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS [patent_app_type] => utility [patent_app_number] => 19/084432 [patent_app_country] => US [patent_app_date] => 2025-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19084432 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/084432
SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS Mar 18, 2025 Pending
Array ( [id] => 20061745 [patent_doc_number] => 20250199967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => Runtime Memory System with Unpredictably Assigned Multiplexed Memory Bus Lines [patent_app_type] => utility [patent_app_number] => 19/070782 [patent_app_country] => US [patent_app_date] => 2025-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19070782 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/070782
Runtime Memory System with Unpredictably Assigned Multiplexed Memory Bus Lines Mar 4, 2025 Pending
Array ( [id] => 20095159 [patent_doc_number] => 20250225095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => HIGH BANDWIDTH THREE-DIMENSIONAL SYSTEM-ON-CHIP [patent_app_type] => utility [patent_app_number] => 19/070373 [patent_app_country] => US [patent_app_date] => 2025-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19070373 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/070373
HIGH BANDWIDTH THREE-DIMENSIONAL SYSTEM-ON-CHIP Mar 3, 2025 Pending
Array ( [id] => 20052165 [patent_doc_number] => 20250190387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => COMPUTER SYSTEM AND A COMPUTER DEVICE [patent_app_type] => utility [patent_app_number] => 19/060470 [patent_app_country] => US [patent_app_date] => 2025-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060470 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/060470
COMPUTER SYSTEM AND A COMPUTER DEVICE Feb 20, 2025 Pending
Array ( [id] => 20070567 [patent_doc_number] => 20250208789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => DETERMINISTIC NEAR-COMPUTE MEMORY FOR DETERMINISTIC PROCESSOR AND ENHANCED DATA MOVEMENT BETWEEN MEMORY UNITS AND PROCESSING UNITS [patent_app_type] => utility [patent_app_number] => 19/058802 [patent_app_country] => US [patent_app_date] => 2025-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19058802 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/058802
DETERMINISTIC NEAR-COMPUTE MEMORY FOR DETERMINISTIC PROCESSOR AND ENHANCED DATA MOVEMENT BETWEEN MEMORY UNITS AND PROCESSING UNITS Feb 19, 2025 Pending
Array ( [id] => 20027198 [patent_doc_number] => 20250165420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => Stacked Semiconductor Device Assembly in Computer System [patent_app_type] => utility [patent_app_number] => 19/028524 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19028524 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/028524
Stacked Semiconductor Device Assembly in Computer System Jan 16, 2025 Pending
Array ( [id] => 20017893 [patent_doc_number] => 20250156115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MODIFYING PROTOCOLS FOR MULTI-PORTED STORAGE DEVICES OF A STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 19/020747 [patent_app_country] => US [patent_app_date] => 2025-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19020747 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/020747
MODIFYING PROTOCOLS FOR MULTI-PORTED STORAGE DEVICES OF A STORAGE SYSTEM Jan 13, 2025 Pending
Array ( [id] => 20087134 [patent_doc_number] => 20250217070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT [patent_app_type] => utility [patent_app_number] => 19/018093 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018093 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018093
MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT Jan 12, 2025 Pending
Array ( [id] => 19993015 [patent_doc_number] => 20250131237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => ADVANCED WAVELET FILTERING FOR ACCELERATED DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 19/001087 [patent_app_country] => US [patent_app_date] => 2024-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 78369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001087 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001087
ADVANCED WAVELET FILTERING FOR ACCELERATED DEEP LEARNING Dec 23, 2024 Pending
Array ( [id] => 19878551 [patent_doc_number] => 20250110808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PLACEMENT OF COMPUTE AND MEMORY FOR ACCELERATED DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 18/978383 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 96384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18978383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/978383
PLACEMENT OF COMPUTE AND MEMORY FOR ACCELERATED DEEP LEARNING Dec 11, 2024 Pending
Array ( [id] => 19822270 [patent_doc_number] => 20250080477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DYNAMIC ROUTING FOR ACCELERATED DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 18/945169 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 88956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18945169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/945169
DYNAMIC ROUTING FOR ACCELERATED DEEP LEARNING Nov 11, 2024 Pending
Array ( [id] => 19802648 [patent_doc_number] => 20250068573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/943232 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18943232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/943232
MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM Nov 10, 2024 Pending
Array ( [id] => 20017854 [patent_doc_number] => 20250156076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => LOCAL CACHE FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/941799 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/941799
LOCAL CACHE FOR MEMORY DEVICES Nov 7, 2024 Pending
Array ( [id] => 20557114 [patent_doc_number] => 20260056900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => MOTHERBOARD DEVICE AND METHOD FOR DETECTING ADD-IN CARD OF MOTHERBOARD DEVICE [patent_app_type] => utility [patent_app_number] => 18/935837 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935837
MOTHERBOARD DEVICE AND METHOD FOR DETECTING ADD-IN CARD OF MOTHERBOARD DEVICE Nov 3, 2024 Pending
Array ( [id] => 20009443 [patent_doc_number] => 20250147665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR ACCESSING MEMORY WITH DIE-TO-DIE INTERFACES [patent_app_type] => utility [patent_app_number] => 18/935341 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935341
SYSTEMS, METHODS, AND APPARATUS FOR ACCESSING MEMORY WITH DIE-TO-DIE INTERFACES Oct 31, 2024 Pending
Array ( [id] => 20043314 [patent_doc_number] => 20250181536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => CHIPLET WITH ADDRESS REMAPPER BLOCK [patent_app_type] => utility [patent_app_number] => 18/935126 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935126
Chiplet with address remapper block Oct 31, 2024 Issued
Array ( [id] => 19878660 [patent_doc_number] => 20250110917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => MULTI-PROCESSOR DEVICE WITH EXTERNAL INTERFACE FAILOVER [patent_app_type] => utility [patent_app_number] => 18/919053 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919053 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919053
MULTI-PROCESSOR DEVICE WITH EXTERNAL INTERFACE FAILOVER Oct 16, 2024 Pending
Array ( [id] => 19748018 [patent_doc_number] => 20250036583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/917560 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917560
MEMORY SYSTEM Oct 15, 2024 Pending
Menu