Search

Harry W. Byrne

Examiner (ID: 13380, Phone: (571)270-3308 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824, 4136
Total Applications
1233
Issued Applications
1198
Pending Applications
2
Abandoned Applications
43

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14955379 [patent_doc_number] => 10438969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/972395 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8028 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972395
Semiconductor device and method of fabricating the same May 6, 2018 Issued
Array ( [id] => 14955379 [patent_doc_number] => 10438969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/972395 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8028 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972395
Semiconductor device and method of fabricating the same May 6, 2018 Issued
Array ( [id] => 14955379 [patent_doc_number] => 10438969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/972395 [patent_app_country] => US [patent_app_date] => 2018-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8028 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15972395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/972395
Semiconductor device and method of fabricating the same May 6, 2018 Issued
Array ( [id] => 15488039 [patent_doc_number] => 10559375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Semiconductor device and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/971591 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12032 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971591 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971591
Semiconductor device and operating method thereof May 3, 2018 Issued
Array ( [id] => 14492181 [patent_doc_number] => 10332891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Method and device to reduce finFET SRAM contact resistance [patent_app_type] => utility [patent_app_number] => 15/967471 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4760 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967471
Method and device to reduce finFET SRAM contact resistance Apr 29, 2018 Issued
Array ( [id] => 15045141 [patent_doc_number] => 20190333575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => MEMORY SYSTEM HAVING A SOURCE BIAS CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/966390 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966390
Memory system having a source bias circuit Apr 29, 2018 Issued
Array ( [id] => 14459347 [patent_doc_number] => 10325644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-18 [patent_title] => Pump circuit in a DRAM, and method for generating a pump current [patent_app_type] => utility [patent_app_number] => 15/967069 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6505 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967069 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967069
Pump circuit in a DRAM, and method for generating a pump current Apr 29, 2018 Issued
Array ( [id] => 14445915 [patent_doc_number] => 20190180831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/967572 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967572
Systems and methods for high-performance write operations Apr 29, 2018 Issued
Array ( [id] => 14603085 [patent_doc_number] => 10354736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-16 [patent_title] => Memory failure detection and resource allocation [patent_app_type] => utility [patent_app_number] => 15/966724 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966724
Memory failure detection and resource allocation Apr 29, 2018 Issued
Array ( [id] => 14954793 [patent_doc_number] => 10438673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-08 [patent_title] => Erasing method and storage medium [patent_app_type] => utility [patent_app_number] => 15/964913 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6353 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964913 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964913
Erasing method and storage medium Apr 26, 2018 Issued
Array ( [id] => 14109597 [patent_doc_number] => 20190096474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => STRAP CELL DESIGN FOR STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY [patent_app_type] => utility [patent_app_number] => 15/962409 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/962409
Strap cell design for static random access memory (SRAM) array Apr 24, 2018 Issued
Array ( [id] => 15029939 [patent_doc_number] => 20190325974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => NON-VOLATILE MEMORY DEVICES AND SYSTEMS WITH READ-ONLY MEMORY FEATURES AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/959921 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959921
Non-volatile memory devices and systems with read-only memory features and methods for operating the same Apr 22, 2018 Issued
Array ( [id] => 15672477 [patent_doc_number] => 10600477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Coupling compensation circuitry [patent_app_type] => utility [patent_app_number] => 15/960475 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960475 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960475
Coupling compensation circuitry Apr 22, 2018 Issued
Array ( [id] => 15171405 [patent_doc_number] => 10491218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Clocked miller latch design for improved soft error rate [patent_app_type] => utility [patent_app_number] => 15/952609 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952609 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/952609
Clocked miller latch design for improved soft error rate Apr 12, 2018 Issued
Array ( [id] => 13349157 [patent_doc_number] => 20180226118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => MULTIPLE RANK HIGH BANDWIDTH MEMORY [patent_app_type] => utility [patent_app_number] => 15/944755 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944755 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944755
Multiple rank high bandwidth memory Apr 2, 2018 Issued
Array ( [id] => 14429253 [patent_doc_number] => 10319440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Void control of confined phase change memory [patent_app_type] => utility [patent_app_number] => 15/937176 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8993 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15937176 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/937176
Void control of confined phase change memory Mar 26, 2018 Issued
Array ( [id] => 13201579 [patent_doc_number] => 10115710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-30 [patent_title] => Package including a plurality of stacked semiconductor devices, an interposer and interface connections [patent_app_type] => utility [patent_app_number] => 15/934183 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 8397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/934183
Package including a plurality of stacked semiconductor devices, an interposer and interface connections Mar 22, 2018 Issued
Array ( [id] => 14430183 [patent_doc_number] => 10319907 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Resistive memory device having a template layer [patent_app_type] => utility [patent_app_number] => 15/923992 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 14994 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923992
Resistive memory device having a template layer Mar 15, 2018 Issued
Array ( [id] => 13935679 [patent_doc_number] => 20190051355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/922406 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922406
Semiconductor memory device and operation method thereof Mar 14, 2018 Issued
Array ( [id] => 13627183 [patent_doc_number] => 20180365143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => Data Storage Device and Method for Operating Nonvolatile Memory [patent_app_type] => utility [patent_app_number] => 15/922666 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922666
Data storage device and method for operating nonvolatile memory Mar 14, 2018 Issued
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