Search

Harry W. Byrne

Examiner (ID: 13380, Phone: (571)270-3308 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824, 4136
Total Applications
1233
Issued Applications
1198
Pending Applications
2
Abandoned Applications
43

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13159261 [patent_doc_number] => 10096364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Three-dimensional vertical NOR flash thin-film transistor strings [patent_app_type] => utility [patent_app_number] => 15/837734 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 16725 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837734
Three-dimensional vertical NOR flash thin-film transistor strings Dec 10, 2017 Issued
Array ( [id] => 12256978 [patent_doc_number] => 09929127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Package including a plurality of stacked semiconductor devices an interposer and interface connections' [patent_app_type] => utility [patent_app_number] => 15/836851 [patent_app_country] => US [patent_app_date] => 2017-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 9070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836851 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836851
Package including a plurality of stacked semiconductor devices an interposer and interface connections Dec 8, 2017 Issued
Array ( [id] => 13403605 [patent_doc_number] => 20180253345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/826857 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826857 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826857
Memory systems and operating method thereof Nov 29, 2017 Issued
Array ( [id] => 13920151 [patent_doc_number] => 10204199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Emulation of quantum and quantum-inspired spectrum analysis and superposition with classical transconductor-capacitor circuits [patent_app_type] => utility [patent_app_number] => 15/826115 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 57 [patent_no_of_words] => 15098 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826115
Emulation of quantum and quantum-inspired spectrum analysis and superposition with classical transconductor-capacitor circuits Nov 28, 2017 Issued
Array ( [id] => 12772993 [patent_doc_number] => 20180149499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => METHOD AND APPARATUS FOR MULTI-CHANNEL SENSOR INTERFACE WITH PROGRAMMABLE GAIN, OFFSET AND BIAS [patent_app_type] => utility [patent_app_number] => 15/824217 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824217
Method and apparatus for multi-channel sensor interface with programmable gain, offset and bias Nov 27, 2017 Issued
Array ( [id] => 14009593 [patent_doc_number] => 10223255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Memory apparatus and method of wear-leveling of a memory apparatus [patent_app_type] => utility [patent_app_number] => 15/821291 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6294 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/821291
Memory apparatus and method of wear-leveling of a memory apparatus Nov 21, 2017 Issued
Array ( [id] => 12800065 [patent_doc_number] => 20180158524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => NON-VOLATILE MEMORY APPARATUS INCLUDING VOLTAGE CLAMPING CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/814625 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814625 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814625
Non-volatile memory apparatus including voltage clamping circuit Nov 15, 2017 Issued
Array ( [id] => 13304519 [patent_doc_number] => 20180203796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/813903 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813903 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813903
Nonvolatile memory device and memory system including the same Nov 14, 2017 Issued
Array ( [id] => 13665221 [patent_doc_number] => 10162773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Double data rate (DDR) memory read latency reduction [patent_app_type] => utility [patent_app_number] => 15/813285 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813285 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813285
Double data rate (DDR) memory read latency reduction Nov 14, 2017 Issued
Array ( [id] => 13257271 [patent_doc_number] => 10141333 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => Domain wall control in ferroelectric devices [patent_app_type] => utility [patent_app_number] => 15/807625 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 5203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807625 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807625
Domain wall control in ferroelectric devices Nov 8, 2017 Issued
Array ( [id] => 13666693 [patent_doc_number] => 10163519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Semiconductor device, electronic component, and electronic device [patent_app_type] => utility [patent_app_number] => 15/804295 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 17850 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804295 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804295
Semiconductor device, electronic component, and electronic device Nov 5, 2017 Issued
Array ( [id] => 13256695 [patent_doc_number] => 10141041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => Systems and methods for maintaining refresh operations of memory banks using a shared [patent_app_type] => utility [patent_app_number] => 15/800267 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15580 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800267 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800267
Systems and methods for maintaining refresh operations of memory banks using a shared Oct 31, 2017 Issued
Array ( [id] => 14009515 [patent_doc_number] => 10223216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-05 [patent_title] => Non-volatile storage system that reclaims bad blocks [patent_app_type] => utility [patent_app_number] => 15/798029 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 13460 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798029
Non-volatile storage system that reclaims bad blocks Oct 29, 2017 Issued
Array ( [id] => 12241286 [patent_doc_number] => 20180074149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'USE OF NUCLEAR SPIN IMPURITIES TO SUPPRESS ELECTRONIC SPIN FLUCTUATIONS AND DECOHERENCE IN COMPOSITE SOLID-STATE SPIN SYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/790007 [patent_app_country] => US [patent_app_date] => 2017-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8782 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790007 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/790007
Use of nuclear spin impurities to suppress electronic spin fluctuations and decoherence in composite solid-state spin systems Oct 21, 2017 Issued
Array ( [id] => 12181428 [patent_doc_number] => 20180040364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/789597 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6895 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789597 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789597
Memory device Oct 19, 2017 Issued
Array ( [id] => 12214682 [patent_doc_number] => 09911497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-06 [patent_title] => 'Three-dimensional vertical NOR flash thin-film transistor strings' [patent_app_type] => utility [patent_app_number] => 15/783201 [patent_app_country] => US [patent_app_date] => 2017-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 17973 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15783201 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/783201
Three-dimensional vertical NOR flash thin-film transistor strings Oct 12, 2017 Issued
Array ( [id] => 12535053 [patent_doc_number] => 10008543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Quantum dot optical devices with enhanced gain and sensitivity and methods of making same [patent_app_type] => utility [patent_app_number] => 15/723190 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 15351 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723190 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723190
Quantum dot optical devices with enhanced gain and sensitivity and methods of making same Oct 2, 2017 Issued
Array ( [id] => 12255983 [patent_doc_number] => 09928126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Recovery from cross-temperature read failures by programming neighbor word lines' [patent_app_type] => utility [patent_app_number] => 15/716684 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 15741 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716684 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716684
Recovery from cross-temperature read failures by programming neighbor word lines Sep 26, 2017 Issued
Array ( [id] => 12154524 [patent_doc_number] => 20180025788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'METHODS OF OPERATING BUFFERED MULTI-RANK MEMORY MODULES CONFIGURED TO SELECTIVELY LINK RANK CONTROL SIGNALS' [patent_app_type] => utility [patent_app_number] => 15/713936 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8120 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713936
Methods of operating buffered multi-rank memory modules configured to selectively link rank control signals Sep 24, 2017 Issued
Array ( [id] => 12477201 [patent_doc_number] => 09990986 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-05 [patent_title] => Static random access memory device having uniform write characteristics [patent_app_type] => utility [patent_app_number] => 15/706859 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706859 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706859
Static random access memory device having uniform write characteristics Sep 17, 2017 Issued
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