
Harry W. Byrne
Examiner (ID: 13380, Phone: (571)270-3308 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824, 4136 |
| Total Applications | 1233 |
| Issued Applications | 1198 |
| Pending Applications | 2 |
| Abandoned Applications | 43 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16323970
[patent_doc_number] => 10783940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 16/799599
[patent_app_country] => US
[patent_app_date] => 2020-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/799599 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Feb 23, 2020 | Issued |
Array
(
[id] => 15917989
[patent_doc_number] => 10656231
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-05-19
[patent_title] => Memory Arrays
[patent_app_type] => utility
[patent_app_number] => 16/799670
[patent_app_country] => US
[patent_app_date] => 2020-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3929
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799670
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/799670 | Memory Arrays | Feb 23, 2020 | Issued |
Array
(
[id] => 16323970
[patent_doc_number] => 10783940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 16/799599
[patent_app_country] => US
[patent_app_date] => 2020-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/799599 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Feb 23, 2020 | Issued |
Array
(
[id] => 16323970
[patent_doc_number] => 10783940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 16/799599
[patent_app_country] => US
[patent_app_date] => 2020-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/799599 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Feb 23, 2020 | Issued |
Array
(
[id] => 16323970
[patent_doc_number] => 10783940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 16/799599
[patent_app_country] => US
[patent_app_date] => 2020-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/799599 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Feb 23, 2020 | Issued |
Array
(
[id] => 16020353
[patent_doc_number] => 20200185020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-11
[patent_title] => APPARATUS AND METHOD FOR CONTROLLING ERASING DATA IN FERROELECTRIC MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 16/793889
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7569
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793889
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793889 | Apparatus and method for controlling erasing data in ferroelectric memory cells | Feb 17, 2020 | Issued |
Array
(
[id] => 16789261
[patent_doc_number] => 10991700
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related memory devices and electronic systems
[patent_app_type] => utility
[patent_app_number] => 16/793888
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 26
[patent_no_of_words] => 13525
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793888
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793888 | Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related memory devices and electronic systems | Feb 17, 2020 | Issued |
Array
(
[id] => 16845762
[patent_doc_number] => 11017856
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-05-25
[patent_title] => Soft reset for multi-level programming of memory cells in non-Von Neumann architectures
[patent_app_type] => utility
[patent_app_number] => 16/793794
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 8769
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793794
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793794 | Soft reset for multi-level programming of memory cells in non-Von Neumann architectures | Feb 17, 2020 | Issued |
Array
(
[id] => 16187107
[patent_doc_number] => 10720448
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Three-dimensional vertical NOR flash thin-film transistor strings
[patent_app_type] => utility
[patent_app_number] => 16/786828
[patent_app_country] => US
[patent_app_date] => 2020-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 34
[patent_no_of_words] => 25096
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786828
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/786828 | Three-dimensional vertical NOR flash thin-film transistor strings | Feb 9, 2020 | Issued |
Array
(
[id] => 16210775
[patent_doc_number] => 20200243765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT CROSS REFERENCES
[patent_app_type] => utility
[patent_app_number] => 16/776391
[patent_app_country] => US
[patent_app_date] => 2020-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6405
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776391
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/776391 | Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references | Jan 28, 2020 | Issued |
Array
(
[id] => 16645301
[patent_doc_number] => 10923165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Stacked memory device, a system including the same and an associated method
[patent_app_type] => utility
[patent_app_number] => 16/743051
[patent_app_country] => US
[patent_app_date] => 2020-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 35
[patent_no_of_words] => 10392
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743051
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/743051 | Stacked memory device, a system including the same and an associated method | Jan 14, 2020 | Issued |
Array
(
[id] => 15872993
[patent_doc_number] => 20200143900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-07
[patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/736537
[patent_app_country] => US
[patent_app_date] => 2020-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12032
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736537
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/736537 | Semiconductor device and operating method thereof | Jan 6, 2020 | Issued |
Array
(
[id] => 15872937
[patent_doc_number] => 20200143872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-07
[patent_title] => METHODS FOR INDEPENDENT MEMORY BANK MAINTENANCE AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/734241
[patent_app_country] => US
[patent_app_date] => 2020-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7382
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734241
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/734241 | Methods for independent memory bank maintenance and memory devices and systems employing the same | Jan 2, 2020 | Issued |
Array
(
[id] => 16552788
[patent_doc_number] => 10885952
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-01-05
[patent_title] => Memory data transfer and switching sequence
[patent_app_type] => utility
[patent_app_number] => 16/727623
[patent_app_country] => US
[patent_app_date] => 2019-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11019
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727623
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/727623 | Memory data transfer and switching sequence | Dec 25, 2019 | Issued |
Array
(
[id] => 16172592
[patent_doc_number] => 10714168
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-14
[patent_title] => Strap cell design for static random access memory (SRAM) array
[patent_app_type] => utility
[patent_app_number] => 16/725409
[patent_app_country] => US
[patent_app_date] => 2019-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 10151
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725409
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/725409 | Strap cell design for static random access memory (SRAM) array | Dec 22, 2019 | Issued |
Array
(
[id] => 16773749
[patent_doc_number] => 10984867
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-04-20
[patent_title] => Direct look ahead mode for memory apparatus programmed with reverse order programming
[patent_app_type] => utility
[patent_app_number] => 16/724876
[patent_app_country] => US
[patent_app_date] => 2019-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 11421
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724876
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/724876 | Direct look ahead mode for memory apparatus programmed with reverse order programming | Dec 22, 2019 | Issued |
Array
(
[id] => 15857459
[patent_doc_number] => 10644029
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-05-05
[patent_title] => Semiconductor device and method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/721740
[patent_app_country] => US
[patent_app_date] => 2019-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 8045
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721740
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/721740 | Semiconductor device and method of fabricating the same | Dec 18, 2019 | Issued |
Array
(
[id] => 16981701
[patent_doc_number] => 20210225938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => VERTICAL 3D MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/771658
[patent_app_country] => US
[patent_app_date] => 2019-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11004
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16771658
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/771658 | Vertical 3D memory device and method for manufacturing the same | Dec 17, 2019 | Issued |
Array
(
[id] => 15806941
[patent_doc_number] => 20200126613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => DYNAMIC BIT-SCAN TECHNIQUES FOR MEMORY DEVICE PROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 16/717532
[patent_app_country] => US
[patent_app_date] => 2019-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18091
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717532
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/717532 | Dynamic bit-scan techniques for memory device programming | Dec 16, 2019 | Issued |
Array
(
[id] => 15776055
[patent_doc_number] => 20200119045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICES HAVING PLURALITY OF VERTICAL CHANNEL STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/707616
[patent_app_country] => US
[patent_app_date] => 2019-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13121
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707616
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/707616 | Three-dimensional memory devices having plurality of vertical channel structures | Dec 8, 2019 | Issued |