Search

Hashem Farrokh

Examiner (ID: 384, Phone: (571)272-4193 , Office: P/2131 )

Most Active Art Unit
2138
Art Unit(s)
2131, 2188, 2187, 2138, 2135
Total Applications
1272
Issued Applications
1114
Pending Applications
61
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18795513 [patent_doc_number] => 11829292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-28 [patent_title] => Priority-based cache-line fitting in compressed memory systems of processor-based systems [patent_app_type] => utility [patent_app_number] => 17/572472 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11900 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572472
Priority-based cache-line fitting in compressed memory systems of processor-based systems Jan 9, 2022 Issued
Array ( [id] => 18471406 [patent_doc_number] => 20230205692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD AND APPARATUS FOR LEVERAGING SIMULTANEOUS MULTITHREADING FOR BULK COMPUTE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/561571 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561571
Method and apparatus for leveraging simultaneous multithreading for bulk compute operations Dec 22, 2021 Issued
Array ( [id] => 18463166 [patent_doc_number] => 11687456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-27 [patent_title] => Memory coloring for executing operations in concurrent paths of a graph representing a model [patent_app_type] => utility [patent_app_number] => 17/558393 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558393
Memory coloring for executing operations in concurrent paths of a graph representing a model Dec 20, 2021 Issued
Array ( [id] => 18079395 [patent_doc_number] => 20220405007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/545464 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545464
Memory system and operating method of memory system Dec 7, 2021 Issued
Array ( [id] => 17475730 [patent_doc_number] => 20220083234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => MEMORY SYSTEM CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/536558 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536558
Memory system controlling nonvolatile memory Nov 28, 2021 Issued
Array ( [id] => 18377884 [patent_doc_number] => 20230152971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => PARAMETER REDUNDANCY REDUCTION METHOD [patent_app_type] => utility [patent_app_number] => 17/525999 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525999
Parameter redundancy reduction method Nov 14, 2021 Issued
Array ( [id] => 17430241 [patent_doc_number] => 20220057950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SEMICONDUCTOR DEVICE AND A METHOD FOR CONTROLLING ACCESSING DATA [patent_app_type] => utility [patent_app_number] => 17/517929 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517929
Semiconductor device and a method for controlling accessing data Nov 2, 2021 Issued
Array ( [id] => 17550031 [patent_doc_number] => 20220121373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Process Acceleration For Software Defined Storage [patent_app_type] => utility [patent_app_number] => 17/505890 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505890
Process acceleration for software defined storage Oct 19, 2021 Issued
Array ( [id] => 18262005 [patent_doc_number] => 11609705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Memory detection method and detection apparatus [patent_app_type] => utility [patent_app_number] => 17/451175 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451175 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451175
Memory detection method and detection apparatus Oct 17, 2021 Issued
Array ( [id] => 19848999 [patent_doc_number] => 20250094350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => SYSTEM AND METHOD FOR CACHE POOLING AND EFFICIENT USAGE AND I/O TRANSFER IN DISAGGREGATED AND MULTI-PROCESSOR ARCHITECTURES VIA PROCESSOR INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/293354 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18293354 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/293354
System and method for cache pooling and efficient usage and I/O transfer in disaggregated and multi-processor architectures via processor interconnect Oct 13, 2021 Issued
Array ( [id] => 17446432 [patent_doc_number] => 20220066937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => HARDWARE COHERENCE SIGNALING PROTOCOL [patent_app_type] => utility [patent_app_number] => 17/498921 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498921
Hardware coherence signaling protocol Oct 11, 2021 Issued
Array ( [id] => 18839251 [patent_doc_number] => 11847325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Semiconductor integrated apparatus, operating method thereof and data processing apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/495552 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4286 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495552
Semiconductor integrated apparatus, operating method thereof and data processing apparatus including the same Oct 5, 2021 Issued
Array ( [id] => 18224508 [patent_doc_number] => 20230063502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DETERMINING AVAILABLE RESOURCES FOR STORING DATA [patent_app_type] => utility [patent_app_number] => 17/488205 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488205
Determining available resources for storing data Sep 27, 2021 Issued
Array ( [id] => 19950229 [patent_doc_number] => 12321593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Regular expression filter for Unicode transformation format strings [patent_app_type] => utility [patent_app_number] => 17/486310 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16424 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486310
Regular expression filter for Unicode transformation format strings Sep 26, 2021 Issued
Array ( [id] => 17338160 [patent_doc_number] => 20220004491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => PERFORMING A MEDIA MANAGEMENT OPERATION BASED ON CHANGING A WRITE MODE OF A DATA BLOCK IN A CACHE [patent_app_type] => utility [patent_app_number] => 17/480214 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480214
Performing a media management operation based on changing a write mode of a data block in a cache Sep 20, 2021 Issued
Array ( [id] => 17276631 [patent_doc_number] => 20210382829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => MEMORY SUB-SYSTEM MANAGEMENT OF FIRMWARE BLOCK RECORD AND DEVICE BLOCK RECORD [patent_app_type] => utility [patent_app_number] => 17/410842 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410842
Memory sub-system management of firmware block record and device block record Aug 23, 2021 Issued
Array ( [id] => 18213415 [patent_doc_number] => 20230059679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => REDUCING MEMORY USAGE IN STORING METADATA [patent_app_type] => utility [patent_app_number] => 17/408007 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408007
Reducing memory usage in storing metadata Aug 19, 2021 Issued
Array ( [id] => 18734742 [patent_doc_number] => 11803472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Integrated circuits (IC) employing subsystem shared cache memory for facilitating extension of low-power island (LPI) memory and related methods [patent_app_type] => utility [patent_app_number] => 17/390274 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11632 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390274
Integrated circuits (IC) employing subsystem shared cache memory for facilitating extension of low-power island (LPI) memory and related methods Jul 29, 2021 Issued
Array ( [id] => 20537566 [patent_doc_number] => 12554643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Electronic device, automotive device, and data center [patent_app_type] => utility [patent_app_number] => 17/388072 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388072
Electronic device, automotive device, and data center Jul 28, 2021 Issued
Array ( [id] => 18965817 [patent_doc_number] => 11899582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Efficient memory dump [patent_app_type] => utility [patent_app_number] => 17/383128 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 34314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17383128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/383128
Efficient memory dump Jul 21, 2021 Issued
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