
Hashem Farrokh
Examiner (ID: 211, Phone: (571)272-4193 , Office: P/2131 )
| Most Active Art Unit | 2138 |
| Art Unit(s) | 2187, 2188, 2131, 2138, 2135 |
| Total Applications | 1269 |
| Issued Applications | 1112 |
| Pending Applications | 60 |
| Abandoned Applications | 119 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17422462
[patent_doc_number] => 11255909
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-22
[patent_title] => Method for synchronizing a checking apparatus, and a checking apparatus and a composite system comprising at least two checking apparatuses
[patent_app_type] => utility
[patent_app_number] => 16/229696
[patent_app_country] => US
[patent_app_date] => 2018-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5079
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 614
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229696
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/229696 | Method for synchronizing a checking apparatus, and a checking apparatus and a composite system comprising at least two checking apparatuses | Dec 20, 2018 | Issued |
Array
(
[id] => 19063805
[patent_doc_number] => 11943068
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => User station for a serial bus system and method for error signaling for a message received in a serial bus system
[patent_app_type] => utility
[patent_app_number] => 16/966721
[patent_app_country] => US
[patent_app_date] => 2018-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5746
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16966721
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/966721 | User station for a serial bus system and method for error signaling for a message received in a serial bus system | Dec 17, 2018 | Issued |
Array
(
[id] => 16077543
[patent_doc_number] => 20200192758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => ADAPTIVE DATA AND PARITY PLACEMENT USING COMPRESSION RATIOS OF STORAGE DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/222235
[patent_app_country] => US
[patent_app_date] => 2018-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9892
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222235
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/222235 | Adaptive data and parity placement using compression ratios of storage devices | Dec 16, 2018 | Issued |
Array
(
[id] => 14286407
[patent_doc_number] => 20190140488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => Composite Integrated Circuits and Methods for Wireless Interactions Therewith
[patent_app_type] => utility
[patent_app_number] => 16/220514
[patent_app_country] => US
[patent_app_date] => 2018-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7883
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220514
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/220514 | Composite integrated circuits and methods for wireless interactions therewith | Dec 13, 2018 | Issued |
Array
(
[id] => 16844756
[patent_doc_number] => 11016843
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-25
[patent_title] => Direct-input redundancy scheme with adaptive syndrome decoder
[patent_app_type] => utility
[patent_app_number] => 16/212017
[patent_app_country] => US
[patent_app_date] => 2018-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 19104
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212017
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/212017 | Direct-input redundancy scheme with adaptive syndrome decoder | Dec 5, 2018 | Issued |
Array
(
[id] => 14160949
[patent_doc_number] => 20190107577
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-11
[patent_title] => INSPECTION DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/205765
[patent_app_country] => US
[patent_app_date] => 2018-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3113
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 366
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205765
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/205765 | Inspection device | Nov 29, 2018 | Issued |
Array
(
[id] => 17408961
[patent_doc_number] => 11249845
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Error-correction-detection coding for hybrid memory module
[patent_app_type] => utility
[patent_app_number] => 16/768722
[patent_app_country] => US
[patent_app_date] => 2018-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4967
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16768722
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/768722 | Error-correction-detection coding for hybrid memory module | Nov 29, 2018 | Issued |
Array
(
[id] => 16186057
[patent_doc_number] => 10719389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Enhanced data storage with concatenated inner and outer error correction codes
[patent_app_type] => utility
[patent_app_number] => 16/204022
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4825
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204022
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/204022 | Enhanced data storage with concatenated inner and outer error correction codes | Nov 28, 2018 | Issued |
Array
(
[id] => 15637101
[patent_doc_number] => 10591536
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-03-17
[patent_title] => Apparatuses and methods involving error detection and correction of linear analog circuits
[patent_app_type] => utility
[patent_app_number] => 16/201396
[patent_app_country] => US
[patent_app_date] => 2018-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 8914
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201396
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/201396 | Apparatuses and methods involving error detection and correction of linear analog circuits | Nov 26, 2018 | Issued |
Array
(
[id] => 15027689
[patent_doc_number] => 20190324849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => ERROR CORRECTION CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/199581
[patent_app_country] => US
[patent_app_date] => 2018-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9441
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199581
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/199581 | Error correction circuit and memory system including the same | Nov 25, 2018 | Issued |
Array
(
[id] => 16700612
[patent_doc_number] => 10951232
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-16
[patent_title] => Error correction bit flipping scheme
[patent_app_type] => utility
[patent_app_number] => 16/199773
[patent_app_country] => US
[patent_app_date] => 2018-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14203
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199773
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/199773 | Error correction bit flipping scheme | Nov 25, 2018 | Issued |
Array
(
[id] => 14511643
[patent_doc_number] => 20190199476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-27
[patent_title] => PHY Error Indication Messaging
[patent_app_type] => utility
[patent_app_number] => 16/196763
[patent_app_country] => US
[patent_app_date] => 2018-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6524
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196763
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/196763 | PHY error indication messaging | Nov 19, 2018 | Issued |
Array
(
[id] => 15548947
[patent_doc_number] => 10574269
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-25
[patent_title] => Polar code processing method and device
[patent_app_type] => utility
[patent_app_number] => 16/196600
[patent_app_country] => US
[patent_app_date] => 2018-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 10947
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196600
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/196600 | Polar code processing method and device | Nov 19, 2018 | Issued |
Array
(
[id] => 17456814
[patent_doc_number] => 11271687
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-08
[patent_title] => Method and arrangement for enhanced soft buffer handling
[patent_app_type] => utility
[patent_app_number] => 16/761283
[patent_app_country] => US
[patent_app_date] => 2018-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13430
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16761283
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/761283 | Method and arrangement for enhanced soft buffer handling | Nov 14, 2018 | Issued |
Array
(
[id] => 16637811
[patent_doc_number] => 10916325
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Memory chip and test system including the same
[patent_app_type] => utility
[patent_app_number] => 16/167258
[patent_app_country] => US
[patent_app_date] => 2018-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 10374
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167258
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/167258 | Memory chip and test system including the same | Oct 21, 2018 | Issued |
Array
(
[id] => 15804269
[patent_doc_number] => 20200125277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => IMPLEMENTING DATA REQUESTS WITH QUALITY OF SERVICE INFORMATION
[patent_app_type] => utility
[patent_app_number] => 16/167319
[patent_app_country] => US
[patent_app_date] => 2018-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167319
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/167319 | Implementing data requests with quality of service information | Oct 21, 2018 | Issued |
Array
(
[id] => 15804603
[patent_doc_number] => 20200125444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => STORAGE SYSTEM STRIPE GROUPING USING MULTIPLE LOGICAL UNITS
[patent_app_type] => utility
[patent_app_number] => 16/165037
[patent_app_country] => US
[patent_app_date] => 2018-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8711
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165037
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/165037 | Storage system stripe grouping using multiple logical units | Oct 18, 2018 | Issued |
Array
(
[id] => 14689183
[patent_doc_number] => 20190243707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => MITIGATING AN UNDETECTABLE ERROR WHEN RETRIEVING CRITICAL DATA DURING ERROR HANDLING
[patent_app_type] => utility
[patent_app_number] => 16/164429
[patent_app_country] => US
[patent_app_date] => 2018-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16164429
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/164429 | Mitigating an undetectable error when retrieving critical data during error handling | Oct 17, 2018 | Issued |
Array
(
[id] => 14409959
[patent_doc_number] => 20190170823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-06
[patent_title] => TEST APPARATUS AND TEST METHOD
[patent_app_type] => utility
[patent_app_number] => 16/146701
[patent_app_country] => US
[patent_app_date] => 2018-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4768
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/146701 | Test apparatus and test method | Sep 27, 2018 | Issued |
Array
(
[id] => 15543491
[patent_doc_number] => 10571518
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-02-25
[patent_title] => Limited pin test interface with analog test bus
[patent_app_type] => utility
[patent_app_number] => 16/142237
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 6260
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142237
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/142237 | Limited pin test interface with analog test bus | Sep 25, 2018 | Issued |