Search

Hee Soo Kim

Examiner (ID: 9452, Phone: (571)270-3229 , Office: P/2457 )

Most Active Art Unit
2457
Art Unit(s)
2457, 2157, 2443
Total Applications
679
Issued Applications
517
Pending Applications
45
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13021361 [patent_doc_number] => 10033810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Recovery point objective via dynamic usage of bind segments in a global mirror environment [patent_app_type] => utility [patent_app_number] => 14/957986 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14957986 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/957986
Recovery point objective via dynamic usage of bind segments in a global mirror environment Dec 2, 2015 Issued
Array ( [id] => 10731590 [patent_doc_number] => 20160077740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SYSTEMS AND METHODS FOR ENABLING LOCAL CACHING FOR REMOTE STORAGE DEVICES OVER A NETWORK VIA NVME CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/941396 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6332 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941396 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941396
SYSTEMS AND METHODS FOR ENABLING LOCAL CACHING FOR REMOTE STORAGE DEVICES OVER A NETWORK VIA NVME CONTROLLER Nov 12, 2015 Abandoned
Array ( [id] => 12146530 [patent_doc_number] => 09880783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'System and method for utilization of a shadow data buffer in a host where the shadow data buffer is controlled by external storage controller' [patent_app_type] => utility [patent_app_number] => 14/925619 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11590 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/925619
System and method for utilization of a shadow data buffer in a host where the shadow data buffer is controlled by external storage controller Oct 27, 2015 Issued
Array ( [id] => 11606696 [patent_doc_number] => 20170123999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'EFFICIENT TRANSLATION RELOADS FOR PAGE FAULTS' [patent_app_type] => utility [patent_app_number] => 14/925646 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8630 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/925646
Efficient translation reloads for page faults with host accelerator directly accessing process address space without setting up DMA with driver and kernel by process inheriting hardware context from the host accelerator Oct 27, 2015 Issued
Array ( [id] => 10493887 [patent_doc_number] => 20150378908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'ALLOCATING READ BLOCKS TO A THREAD IN A TRANSACTION USING USER SPECIFIED LOGICAL ADDRESSES' [patent_app_type] => utility [patent_app_number] => 14/848540 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18548 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848540 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/848540
ALLOCATING READ BLOCKS TO A THREAD IN A TRANSACTION USING USER SPECIFIED LOGICAL ADDRESSES Sep 8, 2015 Abandoned
Array ( [id] => 10493879 [patent_doc_number] => 20150378901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'CO-PROCESSOR MEMORY ACCESSES IN A TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 14/825276 [patent_app_country] => US [patent_app_date] => 2015-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 22202 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825276 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/825276
CO-PROCESSOR MEMORY ACCESSES IN A TRANSACTIONAL MEMORY Aug 12, 2015 Abandoned
Array ( [id] => 10493883 [patent_doc_number] => 20150378905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'CO-PROCESSOR MEMORY ACCESSES IN A TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 14/825264 [patent_app_country] => US [patent_app_date] => 2015-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21826 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/825264
Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor Aug 12, 2015 Issued
Array ( [id] => 11516162 [patent_doc_number] => 20170083236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Method and Apparatus for Multiple Accesses in Memory and Storage System' [patent_app_type] => utility [patent_app_number] => 15/310984 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7304 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15310984 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/310984
Method and apparatus for multiple accesses in memory and storage system, wherein the memory return addresses of vertexes that have not been traversed May 12, 2015 Issued
Array ( [id] => 11292410 [patent_doc_number] => 20160342342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND DATA ACCESS METHOD' [patent_app_type] => utility [patent_app_number] => 15/114612 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11329 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15114612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/114612
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND DATA ACCESS METHOD Feb 3, 2015 Abandoned
Array ( [id] => 12060632 [patent_doc_number] => 20170336976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'DETERMINING RESTING TIMES FOR MEMORY BLOCKS' [patent_app_type] => utility [patent_app_number] => 15/535378 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6586 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15535378 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/535378
DETERMINING RESTING TIMES FOR MEMORY BLOCKS Dec 11, 2014 Abandoned
Array ( [id] => 9933792 [patent_doc_number] => 20150081984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL' [patent_app_type] => utility [patent_app_number] => 14/554532 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 24183 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554532
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL Nov 25, 2014 Abandoned
Array ( [id] => 10204173 [patent_doc_number] => 20150089161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL' [patent_app_type] => utility [patent_app_number] => 14/554849 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17763 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554849
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL Nov 25, 2014 Abandoned
Array ( [id] => 10228249 [patent_doc_number] => 20150113242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'RESTRICTING ACCESS TO SENSITIVE DATA IN SYSTEM MEMORY DUMPS' [patent_app_type] => utility [patent_app_number] => 14/501179 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5372 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501179 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501179
RESTRICTING ACCESS TO SENSITIVE DATA IN SYSTEM MEMORY DUMPS Sep 29, 2014 Abandoned
Array ( [id] => 10276042 [patent_doc_number] => 20150161040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'DATA-STORAGE DEVICE AND DATA ERASING METHOD' [patent_app_type] => utility [patent_app_number] => 14/499511 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2694 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499511 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499511
Data storage device and data erasing method wherein after erasing process, predetermined value is written to indicate completion of said erasing method Sep 28, 2014 Issued
Array ( [id] => 10221556 [patent_doc_number] => 20150106550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/499712 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7907 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499712 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499712
Information processing apparatus, method of writing contiguous blocks for secure erease data and writing distributive blocks for non-secure erase data Sep 28, 2014 Issued
Array ( [id] => 10746205 [patent_doc_number] => 20160092356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'INTEGRATED PAGE-SHARING CACHE' [patent_app_type] => utility [patent_app_number] => 14/499765 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2793 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499765 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499765
Integrated page-sharing cache storing a single copy of data where the data is stored in two volumes and propagating changes to the data in the cache back to the two volumes via volume identifiers Sep 28, 2014 Issued
Array ( [id] => 10745964 [patent_doc_number] => 20160092115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'IMPLEMENTING STORAGE POLICIES REGARDING USE OF MEMORY REGIONS' [patent_app_type] => utility [patent_app_number] => 14/499323 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499323 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499323
IMPLEMENTING STORAGE POLICIES REGARDING USE OF MEMORY REGIONS Sep 28, 2014 Abandoned
Array ( [id] => 12213815 [patent_doc_number] => 09910621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-06 [patent_title] => 'Backlogging I/O metadata utilizing counters to monitor write acknowledgements and no acknowledgements' [patent_app_type] => utility [patent_app_number] => 14/499569 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6686 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499569 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499569
Backlogging I/O metadata utilizing counters to monitor write acknowledgements and no acknowledgements Sep 28, 2014 Issued
Array ( [id] => 10493882 [patent_doc_number] => 20150378904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'ALLOCATING READ BLOCKS TO A THREAD IN A TRANSACTION USING USER SPECIFIED LOGICAL ADDRESSES' [patent_app_type] => utility [patent_app_number] => 14/317446 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18550 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317446 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317446
ALLOCATING READ BLOCKS TO A THREAD IN A TRANSACTION USING USER SPECIFIED LOGICAL ADDRESSES Jun 26, 2014 Abandoned
Array ( [id] => 10493917 [patent_doc_number] => 20150378939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'MEMORY MECHANISM FOR PROVIDING SEMAPHORE FUNCTIONALITY IN MULTI-MASTER PROCESSING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/317954 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14317954 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/317954
MEMORY MECHANISM FOR PROVIDING SEMAPHORE FUNCTIONALITY IN MULTI-MASTER PROCESSING ENVIRONMENT Jun 26, 2014 Abandoned
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