Search

Hee Soo Kim

Examiner (ID: 9452, Phone: (571)270-3229 , Office: P/2457 )

Most Active Art Unit
2457
Art Unit(s)
2457, 2157, 2443
Total Applications
679
Issued Applications
517
Pending Applications
45
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17682498 [patent_doc_number] => 11366752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Address mapping between shared memory modules and cache sets [patent_app_type] => utility [patent_app_number] => 16/824621 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13554 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824621
Address mapping between shared memory modules and cache sets Mar 18, 2020 Issued
Array ( [id] => 17352141 [patent_doc_number] => 11226778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Method, apparatus and computer program product for managing metadata migration [patent_app_type] => utility [patent_app_number] => 16/821404 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7135 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821404
Method, apparatus and computer program product for managing metadata migration Mar 16, 2020 Issued
Array ( [id] => 17621765 [patent_doc_number] => 11340819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Method, device and computer program product for locking at least two address references pointing to storage block in raid type conversion [patent_app_type] => utility [patent_app_number] => 16/821398 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821398 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821398
Method, device and computer program product for locking at least two address references pointing to storage block in raid type conversion Mar 16, 2020 Issued
Array ( [id] => 16802136 [patent_doc_number] => 10997080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Method and system for address table cache management based on correlation metric of first logical address and second logical address, wherein the correlation metric is incremented and decremented based on receive order of the first logical address and the second logical address [patent_app_type] => utility [patent_app_number] => 16/788117 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14785 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788117
Method and system for address table cache management based on correlation metric of first logical address and second logical address, wherein the correlation metric is incremented and decremented based on receive order of the first logical address and the second logical address Feb 10, 2020 Issued
Array ( [id] => 16600250 [patent_doc_number] => 20210026781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => STORAGE DEVICE CONFIGURABLE MAPPING GRANULARITY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/750594 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16750594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/750594
Storage device configurable mapping granularity system where data is written without performing read-modify-write operations Jan 22, 2020 Issued
Array ( [id] => 17309122 [patent_doc_number] => 11210233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => System and method for handling address translation invalidations using an address translation invalidation probe [patent_app_type] => utility [patent_app_number] => 16/736531 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12166 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736531
System and method for handling address translation invalidations using an address translation invalidation probe Jan 6, 2020 Issued
Array ( [id] => 16918786 [patent_doc_number] => 20210191878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => PAGE TABLE MAPPING MECHANISM [patent_app_type] => utility [patent_app_number] => 16/724804 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724804
PAGE TABLE MAPPING MECHANISM Dec 22, 2019 Abandoned
Array ( [id] => 15773173 [patent_doc_number] => 20200117604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => FLUSHING ENTRIES IN A CACHE [patent_app_type] => utility [patent_app_number] => 16/714111 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714111
Flushing entries in a cache by first checking an overflow indicator to determine whether to check a dirty bit of each cache entry Dec 12, 2019 Issued
Array ( [id] => 17606007 [patent_doc_number] => 11334496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Method and system for providing processor-addressable persistent memory to guest operating systems in a storage system [patent_app_type] => utility [patent_app_number] => 16/705307 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5244 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705307
Method and system for providing processor-addressable persistent memory to guest operating systems in a storage system Dec 5, 2019 Issued
Array ( [id] => 16017523 [patent_doc_number] => 20200183605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => EXTENT BASED RAID ENCODING [patent_app_type] => utility [patent_app_number] => 16/703620 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703620
EXTENT BASED RAID ENCODING Dec 3, 2019 Abandoned
Array ( [id] => 17309114 [patent_doc_number] => 11210225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Pre-fetch for memory sub-system with cache where the pre-fetch does not send data and response signal to host [patent_app_type] => utility [patent_app_number] => 16/694605 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694605 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694605
Pre-fetch for memory sub-system with cache where the pre-fetch does not send data and response signal to host Nov 24, 2019 Issued
Array ( [id] => 16849073 [patent_doc_number] => 20210149818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => PROCESS DEDICATED IN-MEMORY TRANSLATION LOOKASIDE BUFFERS (TLBs) (mTLBs) FOR AUGMENTING MEMORY MANAGEMENT UNIT (MMU) TLB FOR TRANSLATING VIRTUAL ADDRESSES (VAs) TO PHYSICAL ADDRESSES (PAs) IN A PROCESSOR-BASED SYSTEM [patent_app_type] => utility [patent_app_number] => 16/685320 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685320
Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system Nov 14, 2019 Issued
Array ( [id] => 17557757 [patent_doc_number] => 11314461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Data storage device and operating method of checking success of garbage collection operation [patent_app_type] => utility [patent_app_number] => 16/658386 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7181 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658386
Data storage device and operating method of checking success of garbage collection operation Oct 20, 2019 Issued
Array ( [id] => 16926964 [patent_doc_number] => 11048447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Providing direct data access between accelerators and storage in a computing environment, wherein the direct data access is independent of host CPU and the host CPU transfers object map identifying object of the data [patent_app_type] => utility [patent_app_number] => 16/656295 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9640 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656295
Providing direct data access between accelerators and storage in a computing environment, wherein the direct data access is independent of host CPU and the host CPU transfers object map identifying object of the data Oct 16, 2019 Issued
Array ( [id] => 17352265 [patent_doc_number] => 11226902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Translation load instruction with access protection [patent_app_type] => utility [patent_app_number] => 16/588380 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6146 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588380
Translation load instruction with access protection Sep 29, 2019 Issued
Array ( [id] => 16729599 [patent_doc_number] => 20210096746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => STORING MULTIPLE DATA VERSIONS IN A DISPERSED STORAGE NETWORK MEMORY [patent_app_type] => utility [patent_app_number] => 16/587951 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587951
Storing difference between current data version and one of multiple data versions in a dispersed storage network memory Sep 29, 2019 Issued
Array ( [id] => 16729813 [patent_doc_number] => 20210096960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SNAPSHOT BLOCK STORAGE PATH STRUCTURE WHEREIN IDENTIFICATION OF BLOCKS THAT ARE IDENTICAL BETWEEN TWO SNAPSHOTS ARE DETERMINED WITHOUT PERFORMING BLOCK BY BLOCK COMPARISON BETWEEN THE TWO SNAPSHOTS [patent_app_type] => utility [patent_app_number] => 16/586640 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586640
Snapshot block storage path structure wherein identification of blocks that are identical between two snapshots are determined without performing block by block comparison between the two snapshots Sep 26, 2019 Issued
Array ( [id] => 16729875 [patent_doc_number] => 20210097022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SUB-BLOCK MODIFICATIONS FOR BLOCK-LEVEL SNAPSHOTS [patent_app_type] => utility [patent_app_number] => 16/586565 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586565
Sub-block modifications for block-level snapshots Sep 26, 2019 Issued
Array ( [id] => 16722079 [patent_doc_number] => 20210089226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => ADAPTIVE WEAR LEVELING FOR DRIVE ARRAYS [patent_app_type] => utility [patent_app_number] => 16/577071 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577071
ADAPTIVE WEAR LEVELING FOR DRIVE ARRAYS Sep 19, 2019 Abandoned
Array ( [id] => 16255597 [patent_doc_number] => 20200264971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => STORAGE SYSTEM AND COMPRESSION METHOD [patent_app_type] => utility [patent_app_number] => 16/570143 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570143 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570143
Storage system and compression method of storing compressed data from storage controller physical address space to logical and physical address space of nonvolatile memory Sep 12, 2019 Issued
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