
Helen C. Kwok
Examiner (ID: 12151, Phone: (571)272-2197 , Office: P/2856 )
| Most Active Art Unit | 2856 |
| Art Unit(s) | 2855, 2856, 2861 |
| Total Applications | 2838 |
| Issued Applications | 2306 |
| Pending Applications | 188 |
| Abandoned Applications | 392 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17660798
[patent_doc_number] => 20220181263
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => INTER-TIER POWER DELIVERY NETWORK (PDN) FOR DENSE GATE-ON-GATE 3D LOGIC INTEGRATION
[patent_app_type] => utility
[patent_app_number] => 17/541561
[patent_app_country] => US
[patent_app_date] => 2021-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5467
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541561
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/541561 | Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration | Dec 2, 2021 | Issued |
Array
(
[id] => 17464093
[patent_doc_number] => 20220077399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => ORGANIC LIGHT-EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/530403
[patent_app_country] => US
[patent_app_date] => 2021-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21473
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2095
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530403
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/530403 | Organic light-emitting device | Nov 17, 2021 | Issued |
Array
(
[id] => 18835379
[patent_doc_number] => 20230403906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => DEPTH MEASUREMENT THROUGH DISPLAY
[patent_app_type] => utility
[patent_app_number] => 18/251029
[patent_app_country] => US
[patent_app_date] => 2021-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 32384
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18251029
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/251029 | DEPTH MEASUREMENT THROUGH DISPLAY | Nov 11, 2021 | Pending |
Array
(
[id] => 17403180
[patent_doc_number] => 20220045271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => PATTERNING OXIDATION RESISTANT ELECTRODE IN CROSSBAR ARRAY CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 17/508660
[patent_app_country] => US
[patent_app_date] => 2021-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3659
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508660
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/508660 | PATTERNING OXIDATION RESISTANT ELECTRODE IN CROSSBAR ARRAY CIRCUITS | Oct 21, 2021 | Pending |
Array
(
[id] => 19810422
[patent_doc_number] => 12241804
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Semiconductor pressure sensor and pressure sensor device
[patent_app_type] => utility
[patent_app_number] => 17/485750
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11478
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485750
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485750 | Semiconductor pressure sensor and pressure sensor device | Sep 26, 2021 | Issued |
Array
(
[id] => 17339367
[patent_doc_number] => 20220005698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-06
[patent_title] => METAL CUT PATTERNING AND ETCHING TO MINIMIZE INTERLAYER DIELECTRIC LAYER LOSS
[patent_app_type] => utility
[patent_app_number] => 17/481516
[patent_app_country] => US
[patent_app_date] => 2021-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10590
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481516
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/481516 | Metal cut patterning and etching to minimize interlayer dielectric layer loss | Sep 21, 2021 | Issued |
Array
(
[id] => 18271783
[patent_doc_number] => 20230093025
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => INCREASED GATE LENGTH AT GIVEN FOOTPRINT FOR NANOSHEET DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/480747
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7589
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480747
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/480747 | Increased gate length at given footprint for nanosheet device | Sep 20, 2021 | Issued |
Array
(
[id] => 18244533
[patent_doc_number] => 20230076844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => SEMICONDUCTOR DIE MODULE PACKAGES WITH VOID-DEFINED SECTIONS IN A METAL STRUCTURE(S) IN A PACKAGE SUBSTRATE TO REDUCE DIE-SUBSTRATE MECHANICAL STRESS, AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 17/470961
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14242
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470961
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/470961 | SEMICONDUCTOR DIE MODULE PACKAGES WITH VOID-DEFINED SECTIONS IN A METAL STRUCTURE(S) IN A PACKAGE SUBSTRATE TO REDUCE DIE-SUBSTRATE MECHANICAL STRESS, AND RELATED METHODS | Sep 8, 2021 | Pending |
Array
(
[id] => 17477520
[patent_doc_number] => 20220085024
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/469984
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7949
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469984
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/469984 | DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF | Sep 8, 2021 | Abandoned |
Array
(
[id] => 18848877
[patent_doc_number] => 20230411281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, MOTOR DRIVE DEVICE, AND VEHICLE
[patent_app_type] => utility
[patent_app_number] => 18/027382
[patent_app_country] => US
[patent_app_date] => 2021-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 97860
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18027382
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/027382 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, MOTOR DRIVE DEVICE, AND VEHICLE | Sep 5, 2021 | Pending |
Array
(
[id] => 17886677
[patent_doc_number] => 20220302155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/446865
[patent_app_country] => US
[patent_app_date] => 2021-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10886
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446865
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/446865 | SEMICONDUCTOR MEMORY DEVICE | Sep 2, 2021 | Abandoned |
Array
(
[id] => 18224792
[patent_doc_number] => 20230063786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR DEVICES WITH FRONT SIDE TO BACKSIDE CONDUCTIVE PATHS AND METHODS OF FABRICATION THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/460482
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11477
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460482
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460482 | SEMICONDUCTOR DEVICES WITH FRONT SIDE TO BACKSIDE CONDUCTIVE PATHS AND METHODS OF FABRICATION THEREOF | Aug 29, 2021 | Issued |
Array
(
[id] => 17933399
[patent_doc_number] => 20220328525
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/461187
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14894
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461187
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/461187 | Semiconductor memory devices and methods of manufacturing thereof | Aug 29, 2021 | Issued |
Array
(
[id] => 17780166
[patent_doc_number] => 20220246516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => SEMICONDUCTOR DEVICE AND SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/460468
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8008
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460468
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460468 | Semiconductor device and substrate | Aug 29, 2021 | Issued |
Array
(
[id] => 18224301
[patent_doc_number] => 20230063295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => PACKAGE STRUCTURE WITH STIFFENER RING HAVING SLANT SIDEWALL
[patent_app_type] => utility
[patent_app_number] => 17/458568
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6967
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458568
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/458568 | PACKAGE STRUCTURE WITH STIFFENER RING HAVING SLANT SIDEWALL | Aug 26, 2021 | Pending |
Array
(
[id] => 17886523
[patent_doc_number] => 20220302001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/411950
[patent_app_country] => US
[patent_app_date] => 2021-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3953
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411950
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/411950 | Semiconductor package and semiconductor device | Aug 24, 2021 | Issued |
Array
(
[id] => 17359945
[patent_doc_number] => 20220020741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => Back Biasing of FD-SOI Circuit Block
[patent_app_type] => utility
[patent_app_number] => 17/410600
[patent_app_country] => US
[patent_app_date] => 2021-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4086
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410600
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/410600 | Back Biasing of FD-SOI Circuit Block | Aug 23, 2021 | Pending |
Array
(
[id] => 17417059
[patent_doc_number] => 20220051963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-17
[patent_title] => Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure
[patent_app_type] => utility
[patent_app_number] => 17/400149
[patent_app_country] => US
[patent_app_date] => 2021-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8571
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400149
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/400149 | Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure | Aug 11, 2021 | Issued |
Array
(
[id] => 19444577
[patent_doc_number] => 12094868
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-17
[patent_title] => Shielded deep trench capacitor structure and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/394489
[patent_app_country] => US
[patent_app_date] => 2021-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 8432
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394489
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/394489 | Shielded deep trench capacitor structure and methods of forming the same | Aug 4, 2021 | Issued |
Array
(
[id] => 18548395
[patent_doc_number] => 11721757
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-08
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/391048
[patent_app_country] => US
[patent_app_date] => 2021-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2834
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391048
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/391048 | Semiconductor device | Aug 1, 2021 | Issued |