Helen Lee Pezzuto

Array ( [id] => 18513394 [patent_doc_number] => 20230229624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => DETERMINING INTERNODAL PROCESSOR INTERCONNECTIONS IN A DATA-PARALLEL COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/096253 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18407965 [patent_doc_number] => 20230169318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => METHOD AND APPARATUS TO EFFICIENTLY PROCESS AND EXECUTE ARTIFICIAL INTELLIGENCE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/095966 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18981984 [patent_doc_number] => 11907157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Reconfigurable processor circuit architecture [patent_app_type] => utility [patent_app_number] => 18/092247 [patent_app_country] => US [patent_app_date] => 2022-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 77 [patent_no_of_words] => 53896 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20188606 [patent_doc_number] => 12399719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Resource access control [patent_app_type] => utility [patent_app_number] => 18/147103 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18147103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18335030 [patent_doc_number] => 20230126978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => ARTIFICIAL INTELLIGENCE CHIP AND ARTIFICIAL INTELLIGENCE CHIP-BASED DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/069216 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19045716 [patent_doc_number] => 11934829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip [patent_app_type] => utility [patent_app_number] => 18/064119 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 62 [patent_no_of_words] => 58399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20160133 [patent_doc_number] => 12386761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory and routing module for use in a computer system [patent_app_type] => utility [patent_app_number] => 18/061167 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 10356 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19036543 [patent_doc_number] => 20240086358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => PROCESSING ELEMENT ARRAY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/988833 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18348428 [patent_doc_number] => 20230136539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => BRIDGING MODULE, DATA TRANSMISSION SYSTEM, AND DATA TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 17/976860 [patent_app_country] => US [patent_app_date] => 2022-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18348428 [patent_doc_number] => 20230136539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => BRIDGING MODULE, DATA TRANSMISSION SYSTEM, AND DATA TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 17/976860 [patent_app_country] => US [patent_app_date] => 2022-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18348428 [patent_doc_number] => 20230136539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => BRIDGING MODULE, DATA TRANSMISSION SYSTEM, AND DATA TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 17/976860 [patent_app_country] => US [patent_app_date] => 2022-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18348428 [patent_doc_number] => 20230136539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => BRIDGING MODULE, DATA TRANSMISSION SYSTEM, AND DATA TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 17/976860 [patent_app_country] => US [patent_app_date] => 2022-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18803330 [patent_doc_number] => 11836489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Sparse matrix calculations utilizing tightly coupled memory and gather/scatter engine [patent_app_type] => utility [patent_app_number] => 17/973466 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18209253 [patent_doc_number] => 20230055513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => Reconfigurable Processor Circuit Architecture [patent_app_type] => utility [patent_app_number] => 17/967173 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19144448 [patent_doc_number] => 20240143361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => APPARATUS AND METHOD FOR MANAGING DEPRECATED INSTRUCTION SET ARCHITECTURE (ISA) FEATURES [patent_app_type] => utility [patent_app_number] => 17/958336 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 67480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -45 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18957355 [patent_doc_number] => 20240045682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => 8-BIT FLOATING POINT SCALE AND/OR REDUCE INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/958370 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18342840 [patent_doc_number] => 11640319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-02 [patent_title] => Task processing method and apparatus, electronic device and storage medium [patent_app_type] => utility [patent_app_number] => 17/945166 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5481 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19747888 [patent_doc_number] => 20250036453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Method and Apparatus for Optimizing Server System Interrupts, Device and Medium [patent_app_type] => utility [patent_app_number] => 18/721358 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18721358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19015231 [patent_doc_number] => 11922165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Parameter vector value proposal apparatus, parameter vector value proposal method, and parameter optimization method [patent_app_type] => utility [patent_app_number] => 17/942285 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16694 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18866760 [patent_doc_number] => 20230421197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => INTERRUPT DRIVEN RECONFIGURATION OF CONFIGURABLE RECEIVER FRONT END MODULE [patent_app_type] => utility [patent_app_number] => 17/897693 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897693 [rel_patent_id] =>[rel_patent_doc_number] =>)