
Helen Sneed
Examiner (ID: 9480)
| Most Active Art Unit | 1204 |
| Art Unit(s) | 1204, 1107, 1106 |
| Total Applications | 871 |
| Issued Applications | 786 |
| Pending Applications | 3 |
| Abandoned Applications | 82 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7446086
[patent_doc_number] => 20040051184
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'Hermetic chip and method of manufacture'
[patent_app_type] => new
[patent_app_number] => 10/624766
[patent_app_country] => US
[patent_app_date] => 2003-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5267
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 483
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20040051184.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624766
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624766 | Hermetic chip in wafer form | Jul 21, 2003 | Issued |
Array
(
[id] => 1022553
[patent_doc_number] => 06888224
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-03
[patent_title] => 'Methods and systems for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials'
[patent_app_type] => utility
[patent_app_number] => 10/609784
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2419
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/888/06888224.pdf
[firstpage_image] =>[orig_patent_app_number] => 10609784
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/609784 | Methods and systems for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials | Jun 29, 2003 | Issued |
Array
(
[id] => 7295936
[patent_doc_number] => 20040124491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Semiconductor device having high impurity concentration region and low impurity concentration region in side surface of active region'
[patent_app_type] => new
[patent_app_number] => 10/452312
[patent_app_country] => US
[patent_app_date] => 2003-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 11046
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20040124491.pdf
[firstpage_image] =>[orig_patent_app_number] => 10452312
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/452312 | Semiconductor device having high impurity concentration region and low impurity concentration region in side surface of active region | Jun 2, 2003 | Abandoned |
Array
(
[id] => 7441158
[patent_doc_number] => 20040195578
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'AlGalnN light emitting diode'
[patent_app_type] => new
[patent_app_number] => 10/445221
[patent_app_country] => US
[patent_app_date] => 2003-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2240
[patent_no_of_claims] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0195/20040195578.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445221
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445221 | AlGaInN light emitting diode | May 26, 2003 | Issued |
Array
(
[id] => 6699424
[patent_doc_number] => 20030222304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-04
[patent_title] => 'Vertical field effect transistor'
[patent_app_type] => new
[patent_app_number] => 10/445502
[patent_app_country] => US
[patent_app_date] => 2003-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5159
[patent_no_of_claims] => 6
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20030222304.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445502
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445502 | Vertical field effect transistor | May 26, 2003 | Issued |
Array
(
[id] => 7295897
[patent_doc_number] => 20040124464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Power semiconductor device having semiconductor-layer-forming position controlled by ion implantation without using photoresist pattern, and method of manufacturing such power semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/437062
[patent_app_country] => US
[patent_app_date] => 2003-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 137
[patent_figures_cnt] => 137
[patent_no_of_words] => 16904
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0124/20040124464.pdf
[firstpage_image] =>[orig_patent_app_number] => 10437062
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/437062 | Power semiconductor device having semiconductor-layer-forming position controlled by ion implantation without using photoresist pattern, and method of manufacturing such power semiconductor device | May 13, 2003 | Issued |
Array
(
[id] => 7411753
[patent_doc_number] => 20040207044
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Laser trimming with phase shifters'
[patent_app_type] => new
[patent_app_number] => 10/418535
[patent_app_country] => US
[patent_app_date] => 2003-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 2533
[patent_no_of_claims] => 39
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20040207044.pdf
[firstpage_image] =>[orig_patent_app_number] => 10418535
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/418535 | Laser trimming with phase shifters | Apr 17, 2003 | Abandoned |
Array
(
[id] => 1144817
[patent_doc_number] => 06777781
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-17
[patent_title] => 'Base-to-substrate leakage cancellation'
[patent_app_type] => B1
[patent_app_number] => 10/413955
[patent_app_country] => US
[patent_app_date] => 2003-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2838
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/777/06777781.pdf
[firstpage_image] =>[orig_patent_app_number] => 10413955
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/413955 | Base-to-substrate leakage cancellation | Apr 13, 2003 | Issued |
Array
(
[id] => 1140735
[patent_doc_number] => 06781154
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Semiconductor apparatus'
[patent_app_type] => B2
[patent_app_number] => 10/385465
[patent_app_country] => US
[patent_app_date] => 2003-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/06/781/06781154.pdf
[firstpage_image] =>[orig_patent_app_number] => 10385465
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/385465 | Semiconductor apparatus | Mar 11, 2003 | Issued |
Array
(
[id] => 7150152
[patent_doc_number] => 20040171222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-02
[patent_title] => 'System and method for integrating multiple metal gates for CMOS applications'
[patent_app_type] => new
[patent_app_number] => 10/376795
[patent_app_country] => US
[patent_app_date] => 2003-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_claims] => 44
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[pdf_file] => publications/A1/0171/20040171222.pdf
[firstpage_image] =>[orig_patent_app_number] => 10376795
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/376795 | System and method for integrating multiple metal gates for CMOS applications | Feb 26, 2003 | Issued |
Array
(
[id] => 6708949
[patent_doc_number] => 20030168698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-11
[patent_title] => 'Semiconductor devices with multiple isolation structure and methods for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/373445
[patent_app_country] => US
[patent_app_date] => 2003-02-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0168/20030168698.pdf
[firstpage_image] =>[orig_patent_app_number] => 10373445
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/373445 | Semiconductor devices with multiple isolation structure and methods for fabricating the same | Feb 24, 2003 | Issued |
Array
(
[id] => 1107683
[patent_doc_number] => 06808995
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[patent_kind] => B2
[patent_issue_date] => 2004-10-26
[patent_title] => 'Semiconductor device with minimal short-channel effects and low bit-line resistance'
[patent_app_type] => B2
[patent_app_number] => 10/361681
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[patent_app_date] => 2003-02-11
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[firstpage_image] =>[orig_patent_app_number] => 10361681
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/361681 | Semiconductor device with minimal short-channel effects and low bit-line resistance | Feb 10, 2003 | Issued |
Array
(
[id] => 6655770
[patent_doc_number] => 20030132442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-17
[patent_title] => 'Semiconductor device with an ohmic ontact and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/351345
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/351345 | Semiconductor device with an ohmic ontact and method of manufacturing the same | Jan 26, 2003 | Abandoned |
Array
(
[id] => 7304862
[patent_doc_number] => 20040140497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'Single-poly EEPROM on a negatively biased substrate'
[patent_app_type] => new
[patent_app_number] => 10/349066
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[patent_app_date] => 2003-01-22
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[firstpage_image] =>[orig_patent_app_number] => 10349066
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/349066 | Single-poly EEPROM on a negatively biased substrate | Jan 21, 2003 | Issued |
Array
(
[id] => 1092914
[patent_doc_number] => 06825115
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-30
[patent_title] => 'Post silicide laser thermal annealing to avoid dopant deactivation'
[patent_app_type] => B1
[patent_app_number] => 10/341436
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341436 | Post silicide laser thermal annealing to avoid dopant deactivation | Jan 13, 2003 | Issued |
Array
(
[id] => 7456651
[patent_doc_number] => 20040119102
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-24
[patent_title] => 'Self-aligned isolation double-gate FET'
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[patent_app_number] => 10/328285
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[firstpage_image] =>[orig_patent_app_number] => 10328285
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/328285 | Self-aligned isolation double-gate FET | Dec 22, 2002 | Issued |
Array
(
[id] => 7301157
[patent_doc_number] => 20040113134
[patent_country] => US
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[patent_issue_date] => 2004-06-17
[patent_title] => 'USING AN MOS SELECT GATE FOR A PHASE CHANGE MEMORY'
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[patent_app_number] => 10/318705
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/318705 | Using an MOS select gate for a phase change memory | Dec 12, 2002 | Issued |
Array
(
[id] => 1095853
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[patent_title] => 'Structure and method for mounting a small sample in an opening in a larger substrate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/318487 | Structure and method for mounting a small sample in an opening in a larger substrate | Dec 12, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/316944 | Semiconductor device with crenellated channel | Dec 11, 2002 | Issued |
Array
(
[id] => 1239634
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[patent_title] => 'Method of forming self-aligned bipolar transistor'
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[firstpage_image] =>[orig_patent_app_number] => 10300105
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300105 | Method of forming self-aligned bipolar transistor | Nov 19, 2002 | Issued |