
Helen Sneed
Examiner (ID: 9480)
| Most Active Art Unit | 1204 |
| Art Unit(s) | 1204, 1107, 1106 |
| Total Applications | 871 |
| Issued Applications | 786 |
| Pending Applications | 3 |
| Abandoned Applications | 82 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1237217
[patent_doc_number] => 06690071
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-10
[patent_title] => 'Semiconductor device using junction leak current'
[patent_app_type] => B2
[patent_app_number] => 10/292465
[patent_app_country] => US
[patent_app_date] => 2002-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 7205
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/690/06690071.pdf
[firstpage_image] =>[orig_patent_app_number] => 10292465
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/292465 | Semiconductor device using junction leak current | Nov 12, 2002 | Issued |
Array
(
[id] => 7353838
[patent_doc_number] => 20040089926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'Ultra thin semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/292055
[patent_app_country] => US
[patent_app_date] => 2002-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1351
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20040089926.pdf
[firstpage_image] =>[orig_patent_app_number] => 10292055
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/292055 | Ultra thin semiconductor device | Nov 11, 2002 | Abandoned |
Array
(
[id] => 7354000
[patent_doc_number] => 20040089946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'Chip size semiconductor package structure'
[patent_app_type] => new
[patent_app_number] => 10/293126
[patent_app_country] => US
[patent_app_date] => 2002-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2011
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 66
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20040089946.pdf
[firstpage_image] =>[orig_patent_app_number] => 10293126
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/293126 | Chip size semiconductor package structure | Nov 11, 2002 | Abandoned |
Array
(
[id] => 1288569
[patent_doc_number] => 06639280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-28
[patent_title] => 'Semiconductor device and semiconductor chip using SOI substrate'
[patent_app_type] => B2
[patent_app_number] => 10/289295
[patent_app_country] => US
[patent_app_date] => 2002-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2986
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/639/06639280.pdf
[firstpage_image] =>[orig_patent_app_number] => 10289295
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/289295 | Semiconductor device and semiconductor chip using SOI substrate | Nov 6, 2002 | Issued |
Array
(
[id] => 7190006
[patent_doc_number] => 20040084779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Bonding pad metal layer geometry design'
[patent_app_type] => new
[patent_app_number] => 10/284715
[patent_app_country] => US
[patent_app_date] => 2002-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2393
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20040084779.pdf
[firstpage_image] =>[orig_patent_app_number] => 10284715
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/284715 | Bonding pad metal layer geometry design | Oct 30, 2002 | Issued |
Array
(
[id] => 1218004
[patent_doc_number] => 06707117
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-16
[patent_title] => 'Method of providing semiconductor interconnects using silicide exclusion'
[patent_app_type] => B1
[patent_app_number] => 10/285235
[patent_app_country] => US
[patent_app_date] => 2002-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2087
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/707/06707117.pdf
[firstpage_image] =>[orig_patent_app_number] => 10285235
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/285235 | Method of providing semiconductor interconnects using silicide exclusion | Oct 30, 2002 | Issued |
Array
(
[id] => 7371633
[patent_doc_number] => 20040079984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Polysilicon self-aligned contact and a polysilicon common source line and method of forming the same'
[patent_app_type] => new
[patent_app_number] => 10/279916
[patent_app_country] => US
[patent_app_date] => 2002-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2423
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20040079984.pdf
[firstpage_image] =>[orig_patent_app_number] => 10279916
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279916 | Polysilicon self-aligned contact and a polysilicon common source line and method of forming the same | Oct 24, 2002 | Abandoned |
Array
(
[id] => 1291147
[patent_doc_number] => 06630395
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-07
[patent_title] => 'Methods for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials'
[patent_app_type] => B1
[patent_app_number] => 10/280266
[patent_app_country] => US
[patent_app_date] => 2002-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2388
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/630/06630395.pdf
[firstpage_image] =>[orig_patent_app_number] => 10280266
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/280266 | Methods for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials | Oct 23, 2002 | Issued |
Array
(
[id] => 7625110
[patent_doc_number] => 06724060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-20
[patent_title] => 'Semiconductor device with solid state image pickup element'
[patent_app_type] => B2
[patent_app_number] => 10/278906
[patent_app_country] => US
[patent_app_date] => 2002-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 24
[patent_no_of_words] => 7347
[patent_no_of_claims] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/724/06724060.pdf
[firstpage_image] =>[orig_patent_app_number] => 10278906
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/278906 | Semiconductor device with solid state image pickup element | Oct 23, 2002 | Issued |
Array
(
[id] => 1254303
[patent_doc_number] => 06670684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-30
[patent_title] => 'Semiconductor device having line-and-space pattern group'
[patent_app_type] => B2
[patent_app_number] => 10/278756
[patent_app_country] => US
[patent_app_date] => 2002-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 7602
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/670/06670684.pdf
[firstpage_image] =>[orig_patent_app_number] => 10278756
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/278756 | Semiconductor device having line-and-space pattern group | Oct 21, 2002 | Issued |
Array
(
[id] => 6647090
[patent_doc_number] => 20030075779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-24
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/274965
[patent_app_country] => US
[patent_app_date] => 2002-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4192
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20030075779.pdf
[firstpage_image] =>[orig_patent_app_number] => 10274965
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/274965 | Semiconductor device and method for manufacturing the same | Oct 21, 2002 | Abandoned |
Array
(
[id] => 1205479
[patent_doc_number] => 06716689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-06
[patent_title] => 'MOS transistor having a T-shaped gate electrode and method for fabricating the same'
[patent_app_type] => B2
[patent_app_number] => 10/274035
[patent_app_country] => US
[patent_app_date] => 2002-10-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/716/06716689.pdf
[firstpage_image] =>[orig_patent_app_number] => 10274035
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/274035 | MOS transistor having a T-shaped gate electrode and method for fabricating the same | Oct 20, 2002 | Issued |
Array
(
[id] => 6841091
[patent_doc_number] => 20030146438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Light emitting diode having a composite upper electrode'
[patent_app_type] => new
[patent_app_number] => 10/273715
[patent_app_country] => US
[patent_app_date] => 2002-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2594
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20030146438.pdf
[firstpage_image] =>[orig_patent_app_number] => 10273715
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/273715 | Light emitting diode having a composite upper electrode | Oct 17, 2002 | Abandoned |
Array
(
[id] => 7205138
[patent_doc_number] => 20040070065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-15
[patent_title] => 'Controlled impedance for wire bonding interconnects'
[patent_app_type] => new
[patent_app_number] => 10/269586
[patent_app_country] => US
[patent_app_date] => 2002-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1415
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0070/20040070065.pdf
[firstpage_image] =>[orig_patent_app_number] => 10269586
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/269586 | Controlled impedance for wire bonding interconnects | Oct 10, 2002 | Abandoned |
Array
(
[id] => 7278820
[patent_doc_number] => 20040061197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Method and apparatus to fabricate an on-chip decoupling capacitor'
[patent_app_type] => new
[patent_app_number] => 10/261225
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 2671
[patent_no_of_claims] => 34
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20040061197.pdf
[firstpage_image] =>[orig_patent_app_number] => 10261225
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/261225 | Method and apparatus to fabricate an on-chip decoupling capacitor | Sep 29, 2002 | Abandoned |
Array
(
[id] => 1302521
[patent_doc_number] => 06624499
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-23
[patent_title] => 'System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient'
[patent_app_type] => B2
[patent_app_number] => 10/247415
[patent_app_country] => US
[patent_app_date] => 2002-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/624/06624499.pdf
[firstpage_image] =>[orig_patent_app_number] => 10247415
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247415 | System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient | Sep 18, 2002 | Issued |
Array
(
[id] => 1312169
[patent_doc_number] => 06610574
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-26
[patent_title] => 'Process for forming MOSgated device with trench structure and remote contact'
[patent_app_type] => B2
[patent_app_number] => 10/242015
[patent_app_country] => US
[patent_app_date] => 2002-09-11
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/610/06610574.pdf
[firstpage_image] =>[orig_patent_app_number] => 10242015
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/242015 | Process for forming MOSgated device with trench structure and remote contact | Sep 10, 2002 | Issued |
Array
(
[id] => 7380435
[patent_doc_number] => 20040036172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-26
[patent_title] => 'Semiconductor device package with integrated heatspreader'
[patent_app_type] => new
[patent_app_number] => 10/227936
[patent_app_country] => US
[patent_app_date] => 2002-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0036/20040036172.pdf
[firstpage_image] =>[orig_patent_app_number] => 10227936
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227936 | Semiconductor device package with integrated heatspreader | Aug 25, 2002 | Abandoned |
Array
(
[id] => 994011
[patent_doc_number] => 06917112
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-12
[patent_title] => 'Conductive semiconductor structures containing metal oxide regions'
[patent_app_type] => utility
[patent_app_number] => 10/227662
[patent_app_country] => US
[patent_app_date] => 2002-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/917/06917112.pdf
[firstpage_image] =>[orig_patent_app_number] => 10227662
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227662 | Conductive semiconductor structures containing metal oxide regions | Aug 25, 2002 | Issued |
| 10/064705 | Semiconductor device and manufacture method thereof | Aug 7, 2002 | Abandoned |