
Helen Sneed
Examiner (ID: 9480)
| Most Active Art Unit | 1204 |
| Art Unit(s) | 1204, 1107, 1106 |
| Total Applications | 871 |
| Issued Applications | 786 |
| Pending Applications | 3 |
| Abandoned Applications | 82 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1006002
[patent_doc_number] => 06906384
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'Semiconductor device having one of patterned SOI and SON structure'
[patent_app_type] => utility
[patent_app_number] => 10/096655
[patent_app_country] => US
[patent_app_date] => 2002-03-14
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/906/06906384.pdf
[firstpage_image] =>[orig_patent_app_number] => 10096655
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/096655 | Semiconductor device having one of patterned SOI and SON structure | Mar 13, 2002 | Issued |
Array
(
[id] => 5968502
[patent_doc_number] => 20020090771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-11
[patent_title] => 'Self-align offset gate structure and method of manufacture'
[patent_app_type] => new
[patent_app_number] => 10/098842
[patent_app_country] => US
[patent_app_date] => 2002-03-13
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[pdf_file] => publications/A1/0090/20020090771.pdf
[firstpage_image] =>[orig_patent_app_number] => 10098842
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/098842 | Self-align offset gate structure and method of manufacture | Mar 12, 2002 | Abandoned |
Array
(
[id] => 6845361
[patent_doc_number] => 20030164528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-04
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING HETERO GRAIN STACK GATE'
[patent_app_type] => new
[patent_app_number] => 10/086565
[patent_app_country] => US
[patent_app_date] => 2002-03-04
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[firstpage_image] =>[orig_patent_app_number] => 10086565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/086565 | Semiconductor device having hetero grain stack gate | Mar 3, 2002 | Issued |
Array
(
[id] => 6506576
[patent_doc_number] => 20020135020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-26
[patent_title] => 'Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor'
[patent_app_type] => new
[patent_app_number] => 10/084255
[patent_app_country] => US
[patent_app_date] => 2002-02-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0135/20020135020.pdf
[firstpage_image] =>[orig_patent_app_number] => 10084255
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/084255 | Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor | Feb 26, 2002 | Issued |
Array
(
[id] => 5964604
[patent_doc_number] => 20020089037
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[patent_kind] => A1
[patent_issue_date] => 2002-07-11
[patent_title] => 'Semiconductor memory device and method for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/076238
[patent_app_country] => US
[patent_app_date] => 2002-02-13
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10076238
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/076238 | Semiconductor memory device and method for manufacturing the same | Feb 12, 2002 | Abandoned |
Array
(
[id] => 6506336
[patent_doc_number] => 20020134998
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[patent_kind] => A1
[patent_issue_date] => 2002-09-26
[patent_title] => 'Semiconductor devices and their peripheral termination'
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[firstpage_image] =>[orig_patent_app_number] => 10067205
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/067205 | Semiconductor devices and their peripheral termination | Feb 4, 2002 | Issued |
Array
(
[id] => 1390491
[patent_doc_number] => 06552360
[patent_country] => US
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[patent_issue_date] => 2003-04-22
[patent_title] => 'Method and circuit layout for reducing post chemical mechanical polishing defect count'
[patent_app_type] => B1
[patent_app_number] => 10/054985
[patent_app_country] => US
[patent_app_date] => 2002-01-25
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[pdf_file] => patents/06/552/06552360.pdf
[firstpage_image] =>[orig_patent_app_number] => 10054985
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/054985 | Method and circuit layout for reducing post chemical mechanical polishing defect count | Jan 24, 2002 | Issued |
Array
(
[id] => 6075966
[patent_doc_number] => 20020079516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-27
[patent_title] => 'Cross-coupled transistor pair'
[patent_app_type] => new
[patent_app_number] => 10/008705
[patent_app_country] => US
[patent_app_date] => 2001-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 5563
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[pdf_file] => publications/A1/0079/20020079516.pdf
[firstpage_image] =>[orig_patent_app_number] => 10008705
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/008705 | Cross-coupled transistor pair | Dec 5, 2001 | Issued |
Array
(
[id] => 6405675
[patent_doc_number] => 20020037598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-28
[patent_title] => 'High frequency, low cost package for semiconductor devices'
[patent_app_type] => new
[patent_app_number] => 09/998241
[patent_app_country] => US
[patent_app_date] => 2001-12-03
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[patent_drawing_sheets_cnt] => 17
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[firstpage_image] =>[orig_patent_app_number] => 09998241
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/998241 | High frequency, low cost package for semiconductor devices | Dec 2, 2001 | Abandoned |
Array
(
[id] => 5782802
[patent_doc_number] => 20020158280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Semiconductor memory device and fabrication method therefor'
[patent_app_type] => new
[patent_app_number] => 09/995836
[patent_app_country] => US
[patent_app_date] => 2001-11-29
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[pdf_file] => publications/A1/0158/20020158280.pdf
[firstpage_image] =>[orig_patent_app_number] => 09995836
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/995836 | Semiconductor memory device | Nov 28, 2001 | Issued |
Array
(
[id] => 6153844
[patent_doc_number] => 20020145165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Semiconductor device having electrostatic discharge protector and fabricating method thereof'
[patent_app_type] => new
[patent_app_number] => 09/988756
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[patent_app_date] => 2001-11-20
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[pdf_file] => publications/A1/0145/20020145165.pdf
[firstpage_image] =>[orig_patent_app_number] => 09988756
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/988756 | Semiconductor device having electrostatic discharge protector and fabricating method thereof | Nov 19, 2001 | Abandoned |
Array
(
[id] => 6790100
[patent_doc_number] => 20030085444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-08
[patent_title] => 'Structure and method for forming a faceted opening and a layer filling therein'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/007295 | Structure and method for forming a faceted opening and a layer filling therein | Nov 7, 2001 | Issued |
Array
(
[id] => 1068703
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[patent_title] => 'Method of manufacturing semiconductor device having storage electrode of capacitor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/999150 | Method of manufacturing semiconductor device having storage electrode of capacitor | Oct 30, 2001 | Issued |
Array
(
[id] => 6475861
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/984036 | Semiconductor memory and manufacturing method thereof | Oct 25, 2001 | Abandoned |
Array
(
[id] => 1005904
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[patent_title] => 'Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/136456 | Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure | Oct 23, 2001 | Issued |
Array
(
[id] => 1600517
[patent_doc_number] => 06475908
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[patent_title] => 'Dual metal gate process: metals and their silicides'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/981415 | Dual metal gate process: metals and their silicides | Oct 17, 2001 | Issued |
Array
(
[id] => 7310054
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/398376 | Transistor and display comprising it | Oct 8, 2001 | Issued |
Array
(
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Array
(
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Array
(
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[patent_title] => 'Contact between element to be driven and thin film transistor for supplying power to element to be driven'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/966445 | Contact between element to be driven and thin film transistor for supplying power to element to be driven | Sep 27, 2001 | Issued |