Helen Sneed

Array ( [id] => 6137813 [patent_doc_number] => 20020000605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Method of fabricating high-coupling ratio split gate flash memory cell array' [patent_app_type] => new [patent_app_number] => 09/827056 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000605.pdf [firstpage_image] =>[orig_patent_app_number] => 09827056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1209296 [patent_doc_number] => 06713351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Double diffused field effect transistor having reduced on-resistance' [patent_app_type] => B2 [patent_app_number] => 09/819356 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3609 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713351.pdf [firstpage_image] =>[orig_patent_app_number] => 09819356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7063425 [patent_doc_number] => 20010042877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Ferroelectric thin-film element, sensor, and method for making the ferroelectric thin-film element' [patent_app_type] => new [patent_app_number] => 09/804375 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042877.pdf [firstpage_image] =>[orig_patent_app_number] => 09804375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5856343 [patent_doc_number] => 20020121663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Semiconductor device and method' [patent_app_type] => new [patent_app_number] => 09/798546 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20020121663.pdf [firstpage_image] =>[orig_patent_app_number] => 09798546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6893445 [patent_doc_number] => 20010015811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Test structure for metal CMP process control' [patent_app_type] => new [patent_app_number] => 09/789276 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4468 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015811.pdf [firstpage_image] =>[orig_patent_app_number] => 09789276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1381773 [patent_doc_number] => 06551885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Low temperature process for a thin film transistor' [patent_app_type] => B1 [patent_app_number] => 09/779986 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551885.pdf [firstpage_image] =>[orig_patent_app_number] => 09779986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634788 [patent_doc_number] => 06656830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Dual damascene with silicon carbide middle etch stop layer/ARC' [patent_app_type] => B1 [patent_app_number] => 09/777695 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3168 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656830.pdf [firstpage_image] =>[orig_patent_app_number] => 09777695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5982024 [patent_doc_number] => 20020096744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in integrated circuits' [patent_app_type] => new [patent_app_number] => 09/768905 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2352 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20020096744.pdf [firstpage_image] =>[orig_patent_app_number] => 09768905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6300427 [patent_doc_number] => 20020093044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof' [patent_app_type] => new [patent_app_number] => 09/761276 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5759 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093044.pdf [firstpage_image] =>[orig_patent_app_number] => 09761276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7090930 [patent_doc_number] => 20010032993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Semiconductor devices and methods for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/759715 [patent_app_country] => US [patent_app_date] => 2001-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10839 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032993.pdf [firstpage_image] =>[orig_patent_app_number] => 09759715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6893099 [patent_doc_number] => 20010015465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Method for forming a transistor for a semiconductior device' [patent_app_type] => new [patent_app_number] => 09/751845 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2825 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015465.pdf [firstpage_image] =>[orig_patent_app_number] => 09751845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1399030 [patent_doc_number] => 06537887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Integrated circuit fabrication' [patent_app_type] => B2 [patent_app_number] => 09/727325 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1165 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537887.pdf [firstpage_image] =>[orig_patent_app_number] => 09727325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645711 [patent_doc_number] => 06472258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Double gate trench transistor' [patent_app_type] => B1 [patent_app_number] => 09/711725 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2573 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472258.pdf [firstpage_image] =>[orig_patent_app_number] => 09711725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1401451 [patent_doc_number] => 06534357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Methods for forming conductive structures and structures regarding same' [patent_app_type] => B1 [patent_app_number] => 09/711206 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6055 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534357.pdf [firstpage_image] =>[orig_patent_app_number] => 09711206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1440004 [patent_doc_number] => 06495403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Gate-all-around semiconductor device and process for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/680035 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3181 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495403.pdf [firstpage_image] =>[orig_patent_app_number] => 09680035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6447525 [patent_doc_number] => 20020177307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Semiconductor device and a method for forming a via hole in a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/490705 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3001 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177307.pdf [firstpage_image] =>[orig_patent_app_number] => 09490705 [rel_patent_id] =>[rel_patent_doc_number] =>)