Search

Henry A. Bennett

Examiner (ID: 890)

Most Active Art Unit
3404
Art Unit(s)
3744, 3743, 2899, 3404
Total Applications
1845
Issued Applications
1679
Pending Applications
49
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18305794 [patent_doc_number] => 20230109694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => INTELLIGENT AUTOMATED FEATURE TOGGLE SYSTEM USING ANNOTATIONS [patent_app_type] => utility [patent_app_number] => 17/497111 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497111
Intelligent automated feature toggle system using annotations Oct 7, 2021 Issued
Array ( [id] => 18119171 [patent_doc_number] => 11550564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-10 [patent_title] => Automating application of software patches to a server having a virtualization layer [patent_app_type] => utility [patent_app_number] => 17/404936 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404936
Automating application of software patches to a server having a virtualization layer Aug 16, 2021 Issued
Array ( [id] => 18276070 [patent_doc_number] => 11615014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Using relocatable debugging information entries to save compile time [patent_app_type] => utility [patent_app_number] => 17/388753 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7362 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388753 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388753
Using relocatable debugging information entries to save compile time Jul 28, 2021 Issued
Array ( [id] => 19182959 [patent_doc_number] => 11989549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Micro-pattern based application modernization assessment [patent_app_type] => utility [patent_app_number] => 17/376546 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376546
Micro-pattern based application modernization assessment Jul 14, 2021 Issued
Array ( [id] => 18839360 [patent_doc_number] => 11847434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Fast search for search string instructions [patent_app_type] => utility [patent_app_number] => 17/356584 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5988 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356584 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356584
Fast search for search string instructions Jun 23, 2021 Issued
Array ( [id] => 18079581 [patent_doc_number] => 20220405193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Runtime Error Prediction System [patent_app_type] => utility [patent_app_number] => 17/354917 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/354917
Runtime Error Prediction System Jun 21, 2021 Abandoned
Array ( [id] => 17024110 [patent_doc_number] => 20210247981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => SYSTEMS AND METHODS FOR OPTIMIZING NESTED LOOP INSTRUCTIONS IN PIPELINE PROCESSING STAGES WITHIN A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/242502 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242502
SYSTEMS AND METHODS FOR OPTIMIZING NESTED LOOP INSTRUCTIONS IN PIPELINE PROCESSING STAGES WITHIN A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT Apr 27, 2021 Abandoned
Array ( [id] => 19107276 [patent_doc_number] => 11960380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Debugging SQL statements [patent_app_type] => utility [patent_app_number] => 17/209888 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209888
Debugging SQL statements Mar 22, 2021 Issued
Array ( [id] => 19369812 [patent_doc_number] => 12061898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Robust firmware and configuration update over network [patent_app_type] => utility [patent_app_number] => 17/203458 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5845 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203458
Robust firmware and configuration update over network Mar 15, 2021 Issued
Array ( [id] => 19443398 [patent_doc_number] => 12093669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-17 [patent_title] => Massively parallel compilation of application code [patent_app_type] => utility [patent_app_number] => 17/196127 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196127
Massively parallel compilation of application code Mar 8, 2021 Issued
Array ( [id] => 18130140 [patent_doc_number] => 11556348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Bootstrapping profile-guided compilation and verification [patent_app_type] => utility [patent_app_number] => 17/181296 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 20396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181296
Bootstrapping profile-guided compilation and verification Feb 21, 2021 Issued
Array ( [id] => 17763493 [patent_doc_number] => 20220237105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => VISUAL DECLARATIVE DEBUGGER [patent_app_type] => utility [patent_app_number] => 17/158655 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158655
Visual declarative debugger Jan 25, 2021 Issued
Array ( [id] => 17636899 [patent_doc_number] => 11347623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => Automated defect type based logging integration within source code [patent_app_type] => utility [patent_app_number] => 17/137717 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137717
Automated defect type based logging integration within source code Dec 29, 2020 Issued
Array ( [id] => 16780727 [patent_doc_number] => 20210117806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => COMPOSABLE NEURAL NETWORK KERNELS [patent_app_type] => utility [patent_app_number] => 17/138709 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138709
Composable neural network kernels Dec 29, 2020 Issued
Array ( [id] => 16903260 [patent_doc_number] => 20210182176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => INTEGRATED DEVELOPMENT ENVIRONMENT TERMINAL, PLATFORM SERVER, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 17/114576 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114576
Integrated development environment terminal, platform server, and medium Dec 7, 2020 Issued
Array ( [id] => 19122340 [patent_doc_number] => 11966322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Preloading debug information based on the increment of application [patent_app_type] => utility [patent_app_number] => 17/104247 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3815 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104247
Preloading debug information based on the increment of application Nov 24, 2020 Issued
Array ( [id] => 16856867 [patent_doc_number] => 20210157612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => ENCACHING AND SHARING TRANSFORMED LIBRARIES [patent_app_type] => utility [patent_app_number] => 17/104320 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104320
Encaching and sharing transformed libraries Nov 24, 2020 Issued
Array ( [id] => 16675753 [patent_doc_number] => 20210064519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => TEST EXECUTION OPTIMIZER FOR TEST AUTOMATION [patent_app_type] => utility [patent_app_number] => 17/035234 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035234
Test execution optimizer for test automation Sep 27, 2020 Issued
Array ( [id] => 18030602 [patent_doc_number] => 11513790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Memory optimized block-based differential update algorithm [patent_app_type] => utility [patent_app_number] => 17/029032 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4251 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029032
Memory optimized block-based differential update algorithm Sep 21, 2020 Issued
Array ( [id] => 16514777 [patent_doc_number] => 20200394035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => Run-Time Application Modification [patent_app_type] => utility [patent_app_number] => 17/003752 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003752
Run-time application modification Aug 25, 2020 Issued
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