Search

Henry C. Yuen

Examiner (ID: 16927)

Most Active Art Unit
3404
Art Unit(s)
3405, 3747, 2899, 3404, 3742, 2602, 3402, 3754
Total Applications
2016
Issued Applications
1698
Pending Applications
3
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11501504 [patent_doc_number] => 20170075689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'METHOD AND APPARATUS FOR EXECUTING CONDITIONAL INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/852898 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7519 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852898 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852898
Method and apparatus for executing conditional instruction predicated on execution result of predicate instruction Sep 13, 2015 Issued
Array ( [id] => 14149387 [patent_doc_number] => 10255074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt [patent_app_type] => utility [patent_app_number] => 14/851238 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8434 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851238 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851238
Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt Sep 10, 2015 Issued
Array ( [id] => 11494360 [patent_doc_number] => 20170068545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'DYNAMIC DETECTION AND CORRECTION OF INCORRECT LOCK AND ATOMIC UPDATE HINT BITS' [patent_app_type] => utility [patent_app_number] => 14/848516 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3901 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/848516
Dynamic detection and correction of incorrect lock and atomic update hint bits Sep 8, 2015 Issued
Array ( [id] => 10493920 [patent_doc_number] => 20150378942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'TRANSACTIONAL EXECUTION ENABLED SUPERVISOR CALL INTERRUPTION WHILE IN TX MODE' [patent_app_type] => utility [patent_app_number] => 14/845350 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 19730 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845350
Transactional execution enabled supervisor call interruption while in TX mode Sep 3, 2015 Issued
Array ( [id] => 11473810 [patent_doc_number] => 20170060593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'HIERARCHICAL REGISTER FILE SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/843921 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10039 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14843921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/843921
HIERARCHICAL REGISTER FILE SYSTEM Sep 1, 2015 Abandoned
Array ( [id] => 11686469 [patent_doc_number] => 09684516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Register renamer that handles multiple register sizes aliased to the same storage locations' [patent_app_type] => utility [patent_app_number] => 14/842915 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842915 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842915
Register renamer that handles multiple register sizes aliased to the same storage locations Sep 1, 2015 Issued
Array ( [id] => 10493771 [patent_doc_number] => 20150378793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'MEMORY PERFORMANCE WHEN SPECULATION CONTROL IS ENABLED, AND INSTRUCTION THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/842949 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 30563 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842949 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842949
Memory performance when speculation control is enabled, and instruction therefor Sep 1, 2015 Issued
Array ( [id] => 13281667 [patent_doc_number] => 10152418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Speculation control for improving transaction success rate, and instruction therefor [patent_app_type] => utility [patent_app_number] => 14/842879 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 25800 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842879 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842879
Speculation control for improving transaction success rate, and instruction therefor Sep 1, 2015 Issued
Array ( [id] => 11473799 [patent_doc_number] => 20170060582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'ARBITRARY INSTRUCTION EXECUTION FROM CONTEXT MEMORY' [patent_app_type] => utility [patent_app_number] => 14/842784 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14842784 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/842784
Arbitrary instruction execution from context memory Aug 31, 2015 Issued
Array ( [id] => 10493717 [patent_doc_number] => 20150378739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'ACCURATE TRACKING OF TRANSACTIONAL READ AND WRITE SETS WITH SPECULATION' [patent_app_type] => utility [patent_app_number] => 14/841790 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 24790 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/841790
Accurate tracking of transactional read and write sets with speculation Aug 31, 2015 Issued
Array ( [id] => 11365925 [patent_doc_number] => 20170003905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'LOCAL INSTRUCTION ORDERING' [patent_app_type] => utility [patent_app_number] => 14/840323 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6922 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840323 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840323
Local ordering of instructions in a computing system Aug 30, 2015 Issued
Array ( [id] => 14364439 [patent_doc_number] => 10303523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Method and apparatus to migrate stacks for thread execution [patent_app_type] => utility [patent_app_number] => 14/836937 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836937 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836937
Method and apparatus to migrate stacks for thread execution Aug 25, 2015 Issued
Array ( [id] => 11423673 [patent_doc_number] => 20170031817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'MULTI-SECTION GARBAGE COLLECTION METHOD' [patent_app_type] => utility [patent_app_number] => 14/833297 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5998 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833297 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833297
Multi-section garbage collection method Aug 23, 2015 Issued
Array ( [id] => 11897135 [patent_doc_number] => 09767071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Execution engine for executing single assignment programs with affine dependencies' [patent_app_type] => utility [patent_app_number] => 14/828470 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8114 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828470 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828470
Execution engine for executing single assignment programs with affine dependencies Aug 16, 2015 Issued
Array ( [id] => 14009597 [patent_doc_number] => 10223257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Multi-section garbage collection [patent_app_type] => utility [patent_app_number] => 14/809852 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5590 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809852 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809852
Multi-section garbage collection Jul 26, 2015 Issued
Array ( [id] => 14427001 [patent_doc_number] => 10318304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Conditional branch prediction using a long history [patent_app_type] => utility [patent_app_number] => 14/809187 [patent_app_country] => US [patent_app_date] => 2015-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10411 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809187 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809187
Conditional branch prediction using a long history Jul 24, 2015 Issued
Array ( [id] => 16032247 [patent_doc_number] => 10678542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Non-shifting reservation station [patent_app_type] => utility [patent_app_number] => 14/808811 [patent_app_country] => US [patent_app_date] => 2015-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7456 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14808811 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/808811
Non-shifting reservation station Jul 23, 2015 Issued
Array ( [id] => 16683270 [patent_doc_number] => 10942748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Method and system for processing interrupts with shadow units in a microcontroller [patent_app_type] => utility [patent_app_number] => 14/800952 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5289 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800952 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800952
Method and system for processing interrupts with shadow units in a microcontroller Jul 15, 2015 Issued
Array ( [id] => 13679487 [patent_doc_number] => 20160378480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations [patent_app_type] => utility [patent_app_number] => 14/752887 [patent_app_country] => US [patent_app_date] => 2015-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752887 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752887
Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations Jun 26, 2015 Abandoned
Array ( [id] => 12331662 [patent_doc_number] => 09946548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Age-based management of instruction blocks in a processor instruction window [patent_app_type] => utility [patent_app_number] => 14/752747 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8291 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752747 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752747
Age-based management of instruction blocks in a processor instruction window Jun 25, 2015 Issued
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