
Henry Choe
Examiner (ID: 6198, Phone: (571)272-1760 , Office: P/2842 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2843, 2842, 2817 |
| Total Applications | 3715 |
| Issued Applications | 3420 |
| Pending Applications | 192 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
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[patent_doc_number] => 07609115
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[patent_title] => 'Input circuitry for transistor power amplifier and method for designing such circuitry'
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Array
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[patent_issue_date] => 2007-12-27
[patent_title] => 'NOISE-SHAPING AMPLIFIER WITH WAVEFORM LOCK'
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Array
(
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[patent_title] => 'METHOD FOR DESIGNING INPUT CIRCUITRY FOR TRANSISTOR POWER AMPLIFIER'
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Array
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[patent_title] => 'Methods for controlling power stage of power amplifier and related apparatuses'
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Array
(
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[patent_title] => 'Technique to improve the gain and signal to noise ratio in CMOS switched capacitor amplifiers'
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Array
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Array
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Array
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Array
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[patent_title] => 'Transconductance signal capacity format'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/843075 | Transconductance signal capacity format | Aug 21, 2007 | Issued |
Array
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[patent_title] => 'TRIPLE CASCODE POWER AMPLIFIER OF INNER PARALLEL CONFIGURATION WITH DYNAMIC GATE BIAS TECHNIQUE'
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Array
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Array
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Array
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Array
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