Henry J. Recla

Array ( [id] => 7446086 [patent_doc_number] => 20040051184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Hermetic chip and method of manufacture' [patent_app_type] => new [patent_app_number] => 10/624766 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5267 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 483 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20040051184.pdf [firstpage_image] =>[orig_patent_app_number] => 10624766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1022553 [patent_doc_number] => 06888224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Methods and systems for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials' [patent_app_type] => utility [patent_app_number] => 10/609784 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2419 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888224.pdf [firstpage_image] =>[orig_patent_app_number] => 10609784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7295936 [patent_doc_number] => 20040124491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Semiconductor device having high impurity concentration region and low impurity concentration region in side surface of active region' [patent_app_type] => new [patent_app_number] => 10/452312 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11046 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124491.pdf [firstpage_image] =>[orig_patent_app_number] => 10452312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6699424 [patent_doc_number] => 20030222304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Vertical field effect transistor' [patent_app_type] => new [patent_app_number] => 10/445502 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5159 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20030222304.pdf [firstpage_image] =>[orig_patent_app_number] => 10445502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7441158 [patent_doc_number] => 20040195578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'AlGalnN light emitting diode' [patent_app_type] => new [patent_app_number] => 10/445221 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2240 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20040195578.pdf [firstpage_image] =>[orig_patent_app_number] => 10445221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7295897 [patent_doc_number] => 20040124464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Power semiconductor device having semiconductor-layer-forming position controlled by ion implantation without using photoresist pattern, and method of manufacturing such power semiconductor device' [patent_app_type] => new [patent_app_number] => 10/437062 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 137 [patent_figures_cnt] => 137 [patent_no_of_words] => 16904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124464.pdf [firstpage_image] =>[orig_patent_app_number] => 10437062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7411753 [patent_doc_number] => 20040207044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Laser trimming with phase shifters' [patent_app_type] => new [patent_app_number] => 10/418535 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2533 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207044.pdf [firstpage_image] =>[orig_patent_app_number] => 10418535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1144817 [patent_doc_number] => 06777781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Base-to-substrate leakage cancellation' [patent_app_type] => B1 [patent_app_number] => 10/413955 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777781.pdf [firstpage_image] =>[orig_patent_app_number] => 10413955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1140735 [patent_doc_number] => 06781154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => B2 [patent_app_number] => 10/385465 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 10527 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781154.pdf [firstpage_image] =>[orig_patent_app_number] => 10385465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7150152 [patent_doc_number] => 20040171222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'System and method for integrating multiple metal gates for CMOS applications' [patent_app_type] => new [patent_app_number] => 10/376795 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4276 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20040171222.pdf [firstpage_image] =>[orig_patent_app_number] => 10376795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6708949 [patent_doc_number] => 20030168698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Semiconductor devices with multiple isolation structure and methods for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/373445 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4524 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20030168698.pdf [firstpage_image] =>[orig_patent_app_number] => 10373445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1107683 [patent_doc_number] => 06808995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Semiconductor device with minimal short-channel effects and low bit-line resistance' [patent_app_type] => B2 [patent_app_number] => 10/361681 [patent_app_country] => US [patent_app_date] => 2003-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2570 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808995.pdf [firstpage_image] =>[orig_patent_app_number] => 10361681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6655770 [patent_doc_number] => 20030132442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Semiconductor device with an ohmic ontact and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/351345 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2879 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20030132442.pdf [firstpage_image] =>[orig_patent_app_number] => 10351345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7304862 [patent_doc_number] => 20040140497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Single-poly EEPROM on a negatively biased substrate' [patent_app_type] => new [patent_app_number] => 10/349066 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3657 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140497.pdf [firstpage_image] =>[orig_patent_app_number] => 10349066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1092914 [patent_doc_number] => 06825115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Post silicide laser thermal annealing to avoid dopant deactivation' [patent_app_type] => B1 [patent_app_number] => 10/341436 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2139 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825115.pdf [firstpage_image] =>[orig_patent_app_number] => 10341436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7456651 [patent_doc_number] => 20040119102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Self-aligned isolation double-gate FET' [patent_app_type] => new [patent_app_number] => 10/328285 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5461 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119102.pdf [firstpage_image] =>[orig_patent_app_number] => 10328285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7301157 [patent_doc_number] => 20040113134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'USING AN MOS SELECT GATE FOR A PHASE CHANGE MEMORY' [patent_app_type] => new [patent_app_number] => 10/318705 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1065 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113134.pdf [firstpage_image] =>[orig_patent_app_number] => 10318705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1095853 [patent_doc_number] => 06821812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Structure and method for mounting a small sample in an opening in a larger substrate' [patent_app_type] => B1 [patent_app_number] => 10/318487 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3915 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821812.pdf [firstpage_image] =>[orig_patent_app_number] => 10318487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1217996 [patent_doc_number] => 06707113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Semiconductor device with crenellated channel' [patent_app_type] => B1 [patent_app_number] => 10/316944 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 3214 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707113.pdf [firstpage_image] =>[orig_patent_app_number] => 10316944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1239634 [patent_doc_number] => 06686250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method of forming self-aligned bipolar transistor' [patent_app_type] => B1 [patent_app_number] => 10/300105 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4049 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686250.pdf [firstpage_image] =>[orig_patent_app_number] => 10300105 [rel_patent_id] =>[rel_patent_doc_number] =>)