Henry J. Recla

Array ( [id] => 8379793 [patent_doc_number] => 20120223422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING' [patent_app_type] => utility [patent_app_number] => 13/040137 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6431 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13040137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8071595 [patent_doc_number] => 20110241228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'EPOXY RESIN COMPOSITION FOR SEALING PACKING OF SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/040034 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6776 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241228.pdf [firstpage_image] =>[orig_patent_app_number] => 13040034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9233331 [patent_doc_number] => 08598639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Si photodiode with symmetry layout and deep well bias in CMOS technology' [patent_app_type] => utility [patent_app_number] => 13/039280 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 2555 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10876832 [patent_doc_number] => 08901622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/038803 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5948 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13038803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6010622 [patent_doc_number] => 20110221019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Silicon-Based Schottky Barrier Detector With Improved Responsivity' [patent_app_type] => utility [patent_app_number] => 13/038470 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3835 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20110221019.pdf [firstpage_image] =>[orig_patent_app_number] => 13038470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8344861 [patent_doc_number] => 20120205784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES' [patent_app_type] => utility [patent_app_number] => 13/037944 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5107 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5932310 [patent_doc_number] => 20110210372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'HIGH-VOLTAGE VERTICAL POWER COMPONENT' [patent_app_type] => utility [patent_app_number] => 13/037694 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2117 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20110210372.pdf [firstpage_image] =>[orig_patent_app_number] => 13037694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8071857 [patent_doc_number] => 20110241099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND FUSE CIRCUIT AND SEMICONDUCTOR MODULE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/038117 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241099.pdf [firstpage_image] =>[orig_patent_app_number] => 13038117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7570931 [patent_doc_number] => 20110266587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/038079 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10628 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266587.pdf [firstpage_image] =>[orig_patent_app_number] => 13038079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8028063 [patent_doc_number] => 08143114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'System and method for source/drain contact processing' [patent_app_type] => utility [patent_app_number] => 13/027436 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/143/08143114.pdf [firstpage_image] =>[orig_patent_app_number] => 13027436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6208374 [patent_doc_number] => 20110133297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS' [patent_app_type] => utility [patent_app_number] => 13/025552 [patent_app_country] => US [patent_app_date] => 2011-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4337 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133297.pdf [firstpage_image] =>[orig_patent_app_number] => 13025552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6208326 [patent_doc_number] => 20110133254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING' [patent_app_type] => utility [patent_app_number] => 13/023959 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3670 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133254.pdf [firstpage_image] =>[orig_patent_app_number] => 13023959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9389872 [patent_doc_number] => 08686475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Reconfigurable elements' [patent_app_type] => utility [patent_app_number] => 13/023796 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 26645 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13023796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6137394 [patent_doc_number] => 20110127609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/022864 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9776 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20110127609.pdf [firstpage_image] =>[orig_patent_app_number] => 13022864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8320713 [patent_doc_number] => 20120193121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'HIGH PERFORMANCE ON-CHIP VERTICAL COAXIAL CABLE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/018963 [patent_app_country] => US [patent_app_date] => 2011-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5092 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6052145 [patent_doc_number] => 20110108849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'TFT-LCD PIXEL UNIT AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/007884 [patent_app_country] => US [patent_app_date] => 2011-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7962 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20110108849.pdf [firstpage_image] =>[orig_patent_app_number] => 13007884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6055205 [patent_doc_number] => 20110111565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'DUAL GATE FINFET' [patent_app_type] => utility [patent_app_number] => 13/006734 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2263 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20110111565.pdf [firstpage_image] =>[orig_patent_app_number] => 13006734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8446776 [patent_doc_number] => 08288831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Semiconductor device, method of manufacturing the same, and electronic device having the same' [patent_app_type] => utility [patent_app_number] => 12/984623 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 12497 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8202891 [patent_doc_number] => 08188549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Semiconductor memory device having layout area reduced' [patent_app_type] => utility [patent_app_number] => 12/984156 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 14401 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/188/08188549.pdf [firstpage_image] =>[orig_patent_app_number] => 12984156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9677529 [patent_doc_number] => 08816440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Low noise and high performance LSI device' [patent_app_type] => utility [patent_app_number] => 12/984261 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 33 [patent_no_of_words] => 10360 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984261 [rel_patent_id] =>[rel_patent_doc_number] =>)