Search

Henry J. Recla

Examiner (ID: 7428)

Most Active Art Unit
3305
Art Unit(s)
3502, 3751, 3700, 3105, 3404, 3731, 3305, 2403
Total Applications
800
Issued Applications
707
Pending Applications
16
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8165792 [patent_doc_number] => 08174091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Fuse structure' [patent_app_type] => utility [patent_app_number] => 12/503641 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174091.pdf [firstpage_image] =>[orig_patent_app_number] => 12503641 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503641
Fuse structure Jul 14, 2009 Issued
Array ( [id] => 5555626 [patent_doc_number] => 20090267203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'MULTI-CHIP PACKAGE FOR REDUCING TEST TIME' [patent_app_type] => utility [patent_app_number] => 12/496576 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2640 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20090267203.pdf [firstpage_image] =>[orig_patent_app_number] => 12496576 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496576
MULTI-CHIP PACKAGE FOR REDUCING TEST TIME Jun 30, 2009 Abandoned
Array ( [id] => 5492828 [patent_doc_number] => 20090260856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'ELECTRONIC COMPONENT MODULE' [patent_app_type] => utility [patent_app_number] => 12/495892 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4864 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20090260856.pdf [firstpage_image] =>[orig_patent_app_number] => 12495892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495892
ELECTRONIC COMPONENT MODULE Jun 30, 2009 Abandoned
Array ( [id] => 8982616 [patent_doc_number] => 08513735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Power semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/127564 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 10050 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13127564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/127564
Power semiconductor device Jun 29, 2009 Issued
Array ( [id] => 6369064 [patent_doc_number] => 20100314735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'Processes and structures for IC fabrication' [patent_app_type] => utility [patent_app_number] => 12/484232 [patent_app_country] => US [patent_app_date] => 2009-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 18160 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314735.pdf [firstpage_image] =>[orig_patent_app_number] => 12484232 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484232
Processes and structures for IC fabrication Jun 13, 2009 Issued
Array ( [id] => 9414095 [patent_doc_number] => 08698132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Functional molecular element, manufacturing method thereof, and functional molecular device' [patent_app_type] => utility [patent_app_number] => 12/999161 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17518 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12999161 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/999161
Functional molecular element, manufacturing method thereof, and functional molecular device Jun 11, 2009 Issued
Array ( [id] => 6097291 [patent_doc_number] => 20110162687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'ORGANIC PHOTOVOLTAIC CELL AND LIGHT EMITTING DIODE WITH AN ARRAY OF 3-DIMENSIONALLY FABRICATED ELECTRODES' [patent_app_type] => utility [patent_app_number] => 12/997241 [patent_app_country] => US [patent_app_date] => 2009-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14220 [patent_no_of_claims] => 119 [patent_no_of_ind_claims] => 100 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20110162687.pdf [firstpage_image] =>[orig_patent_app_number] => 12997241 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/997241
Organic photovoltaic cell and light emitting diode with an array of 3-dimensionally fabricated electrodes Jun 8, 2009 Issued
Array ( [id] => 4526891 [patent_doc_number] => 07952169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Isolation circuit' [patent_app_type] => utility [patent_app_number] => 12/468482 [patent_app_country] => US [patent_app_date] => 2009-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8115 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952169.pdf [firstpage_image] =>[orig_patent_app_number] => 12468482 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/468482
Isolation circuit May 18, 2009 Issued
Array ( [id] => 5539324 [patent_doc_number] => 20090221129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'SEMICONDUCTOR SEAL RING AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/466064 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4885 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20090221129.pdf [firstpage_image] =>[orig_patent_app_number] => 12466064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/466064
Semiconductor seal ring and method of manufacture thereof May 13, 2009 Issued
Array ( [id] => 9166577 [patent_doc_number] => 08592253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Hybrid layers for use in coatings on electronic devices or other articles' [patent_app_type] => utility [patent_app_number] => 12/990860 [patent_app_country] => US [patent_app_date] => 2009-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 13110 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12990860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/990860
Hybrid layers for use in coatings on electronic devices or other articles May 4, 2009 Issued
Array ( [id] => 5402690 [patent_doc_number] => 20090238004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Method of operating sonos memory device' [patent_app_type] => utility [patent_app_number] => 12/453147 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3522 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20090238004.pdf [firstpage_image] =>[orig_patent_app_number] => 12453147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453147
Method of operating a SONOS memory device Apr 29, 2009 Issued
Array ( [id] => 5379863 [patent_doc_number] => 20090191702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/418906 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 8041 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20090191702.pdf [firstpage_image] =>[orig_patent_app_number] => 12418906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/418906
Semiconductor device and manufacturing method thereof Apr 5, 2009 Issued
Array ( [id] => 4624144 [patent_doc_number] => 08003439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Board on chip package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/385316 [patent_app_country] => US [patent_app_date] => 2009-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4196 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003439.pdf [firstpage_image] =>[orig_patent_app_number] => 12385316 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/385316
Board on chip package and manufacturing method thereof Apr 2, 2009 Issued
Array ( [id] => 5530707 [patent_doc_number] => 20090230495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'INPUT DISPLAY' [patent_app_type] => utility [patent_app_number] => 12/417636 [patent_app_country] => US [patent_app_date] => 2009-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20090230495.pdf [firstpage_image] =>[orig_patent_app_number] => 12417636 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/417636
Input display Apr 2, 2009 Issued
Array ( [id] => 6286199 [patent_doc_number] => 20100237462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'Package Level Tuning Techniques for Propagation Channels of High-Speed Signals' [patent_app_type] => utility [patent_app_number] => 12/406265 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237462.pdf [firstpage_image] =>[orig_patent_app_number] => 12406265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/406265
Package Level Tuning Techniques for Propagation Channels of High-Speed Signals Mar 17, 2009 Abandoned
Array ( [id] => 5432110 [patent_doc_number] => 20090166696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'CMOS Image Device with Local Impurity Region' [patent_app_type] => utility [patent_app_number] => 12/395757 [patent_app_country] => US [patent_app_date] => 2009-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3622 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166696.pdf [firstpage_image] =>[orig_patent_app_number] => 12395757 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/395757
CMOS image device with local impurity region Mar 1, 2009 Issued
Array ( [id] => 4431846 [patent_doc_number] => 07968393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Semiconductor device, design method and structure' [patent_app_type] => utility [patent_app_number] => 12/380490 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 54 [patent_no_of_words] => 6422 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968393.pdf [firstpage_image] =>[orig_patent_app_number] => 12380490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/380490
Semiconductor device, design method and structure Feb 25, 2009 Issued
Array ( [id] => 4451595 [patent_doc_number] => 07964920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Semiconductor device, design method and structure' [patent_app_type] => utility [patent_app_number] => 12/380497 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 54 [patent_no_of_words] => 6410 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964920.pdf [firstpage_image] =>[orig_patent_app_number] => 12380497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/380497
Semiconductor device, design method and structure Feb 25, 2009 Issued
Array ( [id] => 5546124 [patent_doc_number] => 20090156001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Structure for reducing stress for vias and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 12/379223 [patent_app_country] => US [patent_app_date] => 2009-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2976 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20090156001.pdf [firstpage_image] =>[orig_patent_app_number] => 12379223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/379223
Structure for reducing stress for vias and fabricating method thereof Feb 16, 2009 Issued
Array ( [id] => 5527283 [patent_doc_number] => 20090197360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'LIGHT EMITTING DIODE PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/370802 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5109 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20090197360.pdf [firstpage_image] =>[orig_patent_app_number] => 12370802 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/370802
Light emitting diode package and fabrication method thereof Feb 12, 2009 Issued
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