Search

Henry W. Yu

Examiner (ID: 15363, Phone: (571)272-9779 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2182, 2181
Total Applications
622
Issued Applications
391
Pending Applications
51
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17031611 [patent_doc_number] => 11093424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Rack switch coupling system [patent_app_type] => utility [patent_app_number] => 16/774345 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9913 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774345 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/774345
Rack switch coupling system Jan 27, 2020 Issued
Array ( [id] => 16299879 [patent_doc_number] => 20200285602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => eUSB2 to USB 2.0 Data Transmission with Surplus Sync Bits [patent_app_type] => utility [patent_app_number] => 16/747719 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747719 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747719
eUSB2 to USB 2.0 Data Transmission with Surplus Sync Bits Jan 20, 2020 Abandoned
Array ( [id] => 16943013 [patent_doc_number] => 11055255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Interface connection apparatus and method [patent_app_type] => utility [patent_app_number] => 16/741932 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3435 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741932
Interface connection apparatus and method Jan 13, 2020 Issued
16/724446 Bucket Update in Data Store Operation Dec 22, 2019 Abandoned
Array ( [id] => 17062014 [patent_doc_number] => 11106616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Virtualized peripheral component interconnect express (PCIe) device [patent_app_type] => utility [patent_app_number] => 16/690212 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16690212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/690212
Virtualized peripheral component interconnect express (PCIe) device Nov 20, 2019 Issued
Array ( [id] => 18262168 [patent_doc_number] => 11609870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Off-module data buffer [patent_app_type] => utility [patent_app_number] => 17/296532 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 8264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/296532
Off-module data buffer Nov 20, 2019 Issued
Array ( [id] => 16895110 [patent_doc_number] => 11036664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Method for determining the transmission speed of a communication module in adapting a connected communication module to a bus and a device for said method [patent_app_type] => utility [patent_app_number] => 16/689609 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 11092 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689609
Method for determining the transmission speed of a communication module in adapting a connected communication module to a bus and a device for said method Nov 19, 2019 Issued
Array ( [id] => 16818787 [patent_doc_number] => 11003617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => USB control circuit utilizing a single configuration pin [patent_app_type] => utility [patent_app_number] => 16/683320 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683320
USB control circuit utilizing a single configuration pin Nov 13, 2019 Issued
Array ( [id] => 17325392 [patent_doc_number] => 11216404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Mechanism for device interoperability of switches in computer buses [patent_app_type] => utility [patent_app_number] => 16/673259 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16048 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673259 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/673259
Mechanism for device interoperability of switches in computer buses Nov 3, 2019 Issued
Array ( [id] => 16121235 [patent_doc_number] => 20200212640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => PERIPHERAL DEVICE [patent_app_type] => utility [patent_app_number] => 16/591594 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591594
Peripheral device Oct 1, 2019 Issued
Array ( [id] => 16454747 [patent_doc_number] => 20200364173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => UNIVERSAL BRIDGE CONTROLLER FOR MACHINE LANGUAGE INTERPRETIVE COLLABORATIVE ROBOT AND MACHINE INTERFACE [patent_app_type] => utility [patent_app_number] => 16/560967 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560967 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560967
UNIVERSAL BRIDGE CONTROLLER FOR MACHINE LANGUAGE INTERPRETIVE COLLABORATIVE ROBOT AND MACHINE INTERFACE Sep 3, 2019 Abandoned
Array ( [id] => 15772461 [patent_doc_number] => 20200117248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => EXTERNAL ELECTRICAL CONNECTOR AND COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 16/533805 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533805
EXTERNAL ELECTRICAL CONNECTOR AND COMPUTER SYSTEM Aug 6, 2019 Abandoned
Array ( [id] => 17589778 [patent_doc_number] => 11328051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => System, methods, and devices responsive to audio signatures [patent_app_type] => utility [patent_app_number] => 16/526447 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526447
System, methods, and devices responsive to audio signatures Jul 29, 2019 Issued
Array ( [id] => 16584867 [patent_doc_number] => 20210019269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => OPTIMIZING TIME-DEPENDENT SIMULATIONS OF QUANTUM COMPUTING ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 16/513215 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513215 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513215
Optimizing time-dependent simulations of quantum computing architectures Jul 15, 2019 Issued
Array ( [id] => 17379989 [patent_doc_number] => 11238005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => SFF-TA-100X based multi-mode protocols solid state devices [patent_app_type] => utility [patent_app_number] => 16/509342 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10639 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509342 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509342
SFF-TA-100X based multi-mode protocols solid state devices Jul 10, 2019 Issued
Array ( [id] => 16592492 [patent_doc_number] => 10901754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Systems and methods for distributed control [patent_app_type] => utility [patent_app_number] => 16/508105 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508105 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508105
Systems and methods for distributed control Jul 9, 2019 Issued
Array ( [id] => 15500737 [patent_doc_number] => 20200050557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Apparatus for Data Processing, Artificial Intelligence Chip and Electronic Device [patent_app_type] => utility [patent_app_number] => 16/506151 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16506151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/506151
Apparatus for data processing, artificial intelligence chip and electronic device Jul 8, 2019 Issued
Array ( [id] => 16737759 [patent_doc_number] => 10963411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture [patent_app_type] => utility [patent_app_number] => 16/502141 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 15376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502141
Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture Jul 2, 2019 Issued
Array ( [id] => 17360759 [patent_doc_number] => 20220021555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => DECENTRALISED COMMUNICATION SYSTEM AND CORRESPONDING CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/413336 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/413336
DECENTRALISED COMMUNICATION SYSTEM AND CORRESPONDING CONTROL METHOD Jun 20, 2019 Abandoned
Array ( [id] => 15854981 [patent_doc_number] => 10642776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Low-pincount high-bandwidth memory and memory bus [patent_app_type] => utility [patent_app_number] => 16/445495 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 84 [patent_figures_cnt] => 84 [patent_no_of_words] => 16524 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445495
Low-pincount high-bandwidth memory and memory bus Jun 18, 2019 Issued
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