Search

Henry W. Yu

Examiner (ID: 13302, Phone: (571)272-9779 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2182, 2181
Total Applications
611
Issued Applications
382
Pending Applications
52
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20101773 [patent_doc_number] => 20250231709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => QUALITY OF SERVICE POLICY SETS [patent_app_type] => utility [patent_app_number] => 18/412912 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412912
Quality of service policy sets Jan 14, 2024 Issued
Array ( [id] => 19283952 [patent_doc_number] => 20240220428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD [patent_app_type] => utility [patent_app_number] => 18/410846 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410846
Memory system design using buffer(s) on a mother board Jan 10, 2024 Issued
Array ( [id] => 19303534 [patent_doc_number] => 20240232114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => RELAY DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/409449 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409449
RELAY DEVICE AND CONTROL METHOD THEREOF Jan 9, 2024 Pending
Array ( [id] => 20018135 [patent_doc_number] => 20250156357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SERVER MOTHERBOARD CONTROL SYSTEM [patent_app_type] => utility [patent_app_number] => 18/406992 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406992
SERVER MOTHERBOARD CONTROL SYSTEM Jan 7, 2024 Pending
Array ( [id] => 19451200 [patent_doc_number] => 20240311330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIE) PHY [patent_app_type] => utility [patent_app_number] => 18/399463 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399463
On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY Dec 27, 2023 Issued
Array ( [id] => 19992739 [patent_doc_number] => 20250130961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => INFRASTRUCTURE INDEPENDENT SELF-CONFIGURING MANAGEMENT NETWORK [patent_app_type] => utility [patent_app_number] => 18/399493 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399493
INFRASTRUCTURE INDEPENDENT SELF-CONFIGURING MANAGEMENT NETWORK Dec 27, 2023 Pending
Array ( [id] => 20061762 [patent_doc_number] => 20250199984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => INDIVIDUAL POWER CYCLE CONTROL OF ACCELERATOR MODULES CONFIGURED ON A NODE [patent_app_type] => utility [patent_app_number] => 18/540113 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/540113
INDIVIDUAL POWER CYCLE CONTROL OF ACCELERATOR MODULES CONFIGURED ON A NODE Dec 13, 2023 Issued
Array ( [id] => 19926932 [patent_doc_number] => 12301231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA) [patent_app_type] => utility [patent_app_number] => 18/536216 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7049 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536216 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536216
Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA) Dec 10, 2023 Issued
Array ( [id] => 19686423 [patent_doc_number] => 20250004968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => POWER TRANSMISSION SYSTEM AND METHOD FOR UNIVERSAL SERIAL BUS RECEPTACLES [patent_app_type] => utility [patent_app_number] => 18/530076 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530076 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530076
POWER TRANSMISSION SYSTEM AND METHOD FOR UNIVERSAL SERIAL BUS RECEPTACLES Dec 4, 2023 Pending
Array ( [id] => 19756660 [patent_doc_number] => 20250045225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => REMOTE MAINTENANCE SYSTEM AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/528824 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528824
REMOTE MAINTENANCE SYSTEM AND OPERATION METHOD THEREOF Dec 4, 2023 Pending
Array ( [id] => 19841576 [patent_doc_number] => 12253963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Prioritization of interfaces of a ventilator [patent_app_type] => utility [patent_app_number] => 18/483741 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483741 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483741
Prioritization of interfaces of a ventilator Oct 9, 2023 Issued
Array ( [id] => 19084898 [patent_doc_number] => 20240111699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SYSTEMS AND METHODS FOR USB SWITCHING IN A COLLABORATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/480382 [patent_app_country] => US [patent_app_date] => 2023-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18480382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/480382
SYSTEMS AND METHODS FOR USB SWITCHING IN A COLLABORATION SYSTEM Oct 2, 2023 Pending
Array ( [id] => 20507202 [patent_doc_number] => 12541478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Apparatus and methods for configuring base address registers [patent_app_type] => utility [patent_app_number] => 18/478288 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 1233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478288
Apparatus and methods for configuring base address registers Sep 28, 2023 Issued
Array ( [id] => 20403601 [patent_doc_number] => 12493574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Techniques for CPU core management based on operation types [patent_app_type] => utility [patent_app_number] => 18/476581 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17277 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476581 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476581
Techniques for CPU core management based on operation types Sep 27, 2023 Issued
Array ( [id] => 20537593 [patent_doc_number] => 12554670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Controlling electrical idle states in retimer outputs [patent_app_type] => utility [patent_app_number] => 18/477470 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/477470
Controlling electrical idle states in retimer outputs Sep 27, 2023 Issued
Array ( [id] => 18867027 [patent_doc_number] => 20230421464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => System, Method and Apparatus for Bridge Interface Communication [patent_app_type] => utility [patent_app_number] => 18/243801 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/243801
System, Method and Apparatus for Bridge Interface Communication Sep 7, 2023 Pending
Array ( [id] => 20550478 [patent_doc_number] => 12561271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Computing systems having congestion monitors therein and methods of controlling operation of same [patent_app_type] => utility [patent_app_number] => 18/460954 [patent_app_country] => US [patent_app_date] => 2023-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 9011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460954 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460954
Computing systems having congestion monitors therein and methods of controlling operation of same Sep 4, 2023 Issued
Array ( [id] => 19819254 [patent_doc_number] => 20250077461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => AUTOMATIC HIGH-SPEED SHUTDOWN FOR C-PHY RECEIVER [patent_app_type] => utility [patent_app_number] => 18/460905 [patent_app_country] => US [patent_app_date] => 2023-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460905
Automatic high-speed shutdown for C-PHY receiver Sep 4, 2023 Issued
Array ( [id] => 19320307 [patent_doc_number] => 20240241851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => DATA TRANSMISSION SYSTEM AND DATA TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 18/460701 [patent_app_country] => US [patent_app_date] => 2023-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460701
DATA TRANSMISSION SYSTEM AND DATA TRANSMISSION METHOD Sep 4, 2023 Abandoned
Array ( [id] => 20273774 [patent_doc_number] => 12443556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => PCI flow control with signal interception [patent_app_type] => utility [patent_app_number] => 18/446107 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2473 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446107 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446107
PCI flow control with signal interception Aug 7, 2023 Issued
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