
Henry W. Yu
Examiner (ID: 15363, Phone: (571)272-9779 , Office: P/2181 )
| Most Active Art Unit | 2181 |
| Art Unit(s) | 2182, 2181 |
| Total Applications | 622 |
| Issued Applications | 391 |
| Pending Applications | 51 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20680241
[patent_doc_number] => 20260119058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-04-30
[patent_title] => MEMORY CAPACITY ADJUSTMENT METHOD AND APPARATUS, AND SERVER, ELECTRONIC DEVICE AND STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 19/166825
[patent_app_country] => US
[patent_app_date] => 2024-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19166825
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/166825 | MEMORY CAPACITY ADJUSTMENT METHOD AND APPARATUS, AND SERVER, ELECTRONIC DEVICE AND STORAGE MEDIUM | May 26, 2024 | Pending |
Array
(
[id] => 20745715
[patent_doc_number] => 12645627
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Fibre channel protocol exchange handling
[patent_app_type] => utility
[patent_app_number] => 18/646206
[patent_app_country] => US
[patent_app_date] => 2024-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2415
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646206
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/646206 | Fibre channel protocol exchange handling | Apr 24, 2024 | Issued |
Array
(
[id] => 20994755
[patent_doc_number] => 12743390
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-09-22
[patent_title] => Circuit board of graphics processing unit and server system
[patent_app_type] => utility
[patent_app_number] => 19/139143
[patent_app_country] => US
[patent_app_date] => 2024-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2608
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 314
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19139143
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/139143 | Circuit Board of Graphics Processing Unit and Server System | Apr 15, 2024 | Pending |
Array
(
[id] => 20290149
[patent_doc_number] => 20250315392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-09
[patent_title] => DYNAMICALLY ROUTING INPUT/OUTPUT COMMANDS
[patent_app_type] => utility
[patent_app_number] => 18/630208
[patent_app_country] => US
[patent_app_date] => 2024-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630208
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/630208 | DYNAMICALLY ROUTING INPUT/OUTPUT COMMANDS | Apr 8, 2024 | Pending |
Array
(
[id] => 19482189
[patent_doc_number] => 20240330231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => COMMUNICATION INTERFACE CHIP AND ADDRESS EXTENSION CIRCUIT THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/616411
[patent_app_country] => US
[patent_app_date] => 2024-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4402
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616411
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/616411 | COMMUNICATION INTERFACE CHIP AND ADDRESS EXTENSION CIRCUIT THEREOF | Mar 25, 2024 | Pending |
Array
(
[id] => 20249898
[patent_doc_number] => 20250298767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => SYSTEMS AND METHODS FOR SELECTING AN OPTIMAL COMMUNICATION PATH IN A HETEROGENEOUS COMPUTING PLATFORM
[patent_app_type] => utility
[patent_app_number] => 18/611765
[patent_app_country] => US
[patent_app_date] => 2024-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11435
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611765
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/611765 | SYSTEMS AND METHODS FOR SELECTING AN OPTIMAL COMMUNICATION PATH IN A HETEROGENEOUS COMPUTING PLATFORM | Mar 20, 2024 | Pending |
Array
(
[id] => 20208652
[patent_doc_number] => 20250278372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-04
[patent_title] => ACCESSING A SECONDARY SHARED RESOURCE USING VIRTUAL IDENTIFIERS
[patent_app_type] => utility
[patent_app_number] => 18/591498
[patent_app_country] => US
[patent_app_date] => 2024-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6046
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591498
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/591498 | Accessing a secondary shared resource using virtual identifiers | Feb 28, 2024 | Issued |
Array
(
[id] => 20673313
[patent_doc_number] => 12613825
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-28
[patent_title] => Parallel RAS channels in CXL memory device
[patent_app_type] => utility
[patent_app_number] => 18/444550
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5767
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444550
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444550 | Parallel RAS channels in CXL memory device | Feb 15, 2024 | Issued |
Array
(
[id] => 20160006
[patent_doc_number] => 12386634
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => Systems and methods for distributed control
[patent_app_type] => utility
[patent_app_number] => 18/440850
[patent_app_country] => US
[patent_app_date] => 2024-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 7818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 369
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440850
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/440850 | Systems and methods for distributed control | Feb 12, 2024 | Issued |
Array
(
[id] => 20790195
[patent_doc_number] => 12664110
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-23
[patent_title] => Input/output device in a high density or rackmount environment
[patent_app_type] => utility
[patent_app_number] => 18/412908
[patent_app_country] => US
[patent_app_date] => 2024-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4714
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412908
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/412908 | Input/output device in a high density or rackmount environment | Jan 14, 2024 | Issued |
Array
(
[id] => 20101773
[patent_doc_number] => 20250231709
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-17
[patent_title] => QUALITY OF SERVICE POLICY SETS
[patent_app_type] => utility
[patent_app_number] => 18/412912
[patent_app_country] => US
[patent_app_date] => 2024-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11380
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412912
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/412912 | Quality of service policy sets | Jan 14, 2024 | Issued |
Array
(
[id] => 19283952
[patent_doc_number] => 20240220428
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
[patent_app_type] => utility
[patent_app_number] => 18/410846
[patent_app_country] => US
[patent_app_date] => 2024-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10664
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410846
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/410846 | Memory system design using buffer(s) on a mother board | Jan 10, 2024 | Issued |
Array
(
[id] => 19303534
[patent_doc_number] => 20240232114
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => RELAY DEVICE AND CONTROL METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/409449
[patent_app_country] => US
[patent_app_date] => 2024-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2311
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409449
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/409449 | RELAY DEVICE AND CONTROL METHOD THEREOF | Jan 9, 2024 | Pending |
Array
(
[id] => 20018135
[patent_doc_number] => 20250156357
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-15
[patent_title] => SERVER MOTHERBOARD CONTROL SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/406992
[patent_app_country] => US
[patent_app_date] => 2024-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406992
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/406992 | SERVER MOTHERBOARD CONTROL SYSTEM | Jan 7, 2024 | Pending |
Array
(
[id] => 19992739
[patent_doc_number] => 20250130961
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-24
[patent_title] => INFRASTRUCTURE INDEPENDENT SELF-CONFIGURING MANAGEMENT NETWORK
[patent_app_type] => utility
[patent_app_number] => 18/399493
[patent_app_country] => US
[patent_app_date] => 2023-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399493
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/399493 | INFRASTRUCTURE INDEPENDENT SELF-CONFIGURING MANAGEMENT NETWORK | Dec 27, 2023 | Pending |
Array
(
[id] => 19451200
[patent_doc_number] => 20240311330
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIE) PHY
[patent_app_type] => utility
[patent_app_number] => 18/399463
[patent_app_country] => US
[patent_app_date] => 2023-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15796
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/399463 | On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY | Dec 27, 2023 | Issued |
Array
(
[id] => 20666555
[patent_doc_number] => 12608330
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-21
[patent_title] => Individual power cycle control of accelerator modules configured on a node
[patent_app_type] => utility
[patent_app_number] => 18/540113
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2185
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540113
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/540113 | Individual power cycle control of accelerator modules configured on a node | Dec 13, 2023 | Issued |
Array
(
[id] => 19926932
[patent_doc_number] => 12301231
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA)
[patent_app_type] => utility
[patent_app_number] => 18/536216
[patent_app_country] => US
[patent_app_date] => 2023-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7049
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536216
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/536216 | Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA) | Dec 10, 2023 | Issued |
Array
(
[id] => 19686423
[patent_doc_number] => 20250004968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => POWER TRANSMISSION SYSTEM AND METHOD FOR UNIVERSAL SERIAL BUS RECEPTACLES
[patent_app_type] => utility
[patent_app_number] => 18/530076
[patent_app_country] => US
[patent_app_date] => 2023-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3429
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530076
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/530076 | POWER TRANSMISSION SYSTEM AND METHOD FOR UNIVERSAL SERIAL BUS RECEPTACLES | Dec 4, 2023 | Pending |
Array
(
[id] => 19756660
[patent_doc_number] => 20250045225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-06
[patent_title] => REMOTE MAINTENANCE SYSTEM AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/528824
[patent_app_country] => US
[patent_app_date] => 2023-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2578
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528824
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/528824 | Remote maintenance system and operation method thereof | Dec 4, 2023 | Issued |