Search

Herbert Kerner

Examiner (ID: 12458)

Most Active Art Unit
2105
Art Unit(s)
2852, 2105
Total Applications
88
Issued Applications
80
Pending Applications
0
Abandoned Applications
8

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10462011 [patent_doc_number] => 20150347026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'METHOD AND SYSTEM FOR INTERLEAVING PIECES OF A MAPPING TABLE FOR A STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/289254 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9401 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14289254 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/289254
Method and system for creating a mapping table cache from an interleaved subset of contiguous mapping data for a storage device May 27, 2014 Issued
Array ( [id] => 11917164 [patent_doc_number] => 09785348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Balancing usage of real and virtual space to avoid out-of-space conditions in storage controllers' [patent_app_type] => utility [patent_app_number] => 14/288689 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6157 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288689 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/288689
Balancing usage of real and virtual space to avoid out-of-space conditions in storage controllers May 27, 2014 Issued
Array ( [id] => 10941516 [patent_doc_number] => 20140344537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'CONTROL METHOD, TRANSMISSION APPARATUS, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/273699 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11967 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273699
Control method, transmission apparatus, and recording medium comparing versions of circuit data and copying to match circuit data of first and second interfaces May 8, 2014 Issued
Array ( [id] => 10439307 [patent_doc_number] => 20150324319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'INTERCONNECT SYSTEMS AND METHODS USING HYBRID MEMORY CUBE LINKS' [patent_app_type] => utility [patent_app_number] => 14/273867 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7541 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273867 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273867
Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device May 8, 2014 Issued
Array ( [id] => 10416924 [patent_doc_number] => 20150301934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'FLASH-BASED DATA STORAGE WITH DUAL MAP-BASED SERIALIZATION' [patent_app_type] => utility [patent_app_number] => 14/273812 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8136 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273812
System, method and computer-readable medium using map tables in a cache to manage write requests to a raid storage array May 8, 2014 Issued
Array ( [id] => 11769488 [patent_doc_number] => 09378152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Systems and methods for I/O processing using out-of-band hinting to block driver or storage controller' [patent_app_type] => utility [patent_app_number] => 14/274153 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274153 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/274153
Systems and methods for I/O processing using out-of-band hinting to block driver or storage controller May 8, 2014 Issued
Array ( [id] => 10439272 [patent_doc_number] => 20150324285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'VIRTUALIZED PHYSICAL ADDRESSES FOR RECONFIGURABLE MEMORY SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/274195 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7878 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274195 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/274195
Protection zones in virtualized physical addresses for reconfigurable memory systems using a memory abstraction May 8, 2014 Issued
Array ( [id] => 11238910 [patent_doc_number] => 09465556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'RAID 0 disk array system and data processing method for dividing reading command to reading command segments and transmitting reading command segments to disks or directly transmitting reading command to one of disks without dividing' [patent_app_type] => utility [patent_app_number] => 14/273528 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3704 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273528 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273528
RAID 0 disk array system and data processing method for dividing reading command to reading command segments and transmitting reading command segments to disks or directly transmitting reading command to one of disks without dividing May 7, 2014 Issued
Array ( [id] => 10550088 [patent_doc_number] => 09274713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Device driver, method and computer-readable medium for dynamically configuring a storage controller based on RAID type, data alignment with a characteristic of storage elements and queue depth in a cache' [patent_app_type] => utility [patent_app_number] => 14/272651 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 13066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272651 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272651
Device driver, method and computer-readable medium for dynamically configuring a storage controller based on RAID type, data alignment with a characteristic of storage elements and queue depth in a cache May 7, 2014 Issued
Array ( [id] => 9688149 [patent_doc_number] => 20140244914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION' [patent_app_type] => utility [patent_app_number] => 14/269299 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6640 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14269299 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/269299
Mitigate flash write latency and bandwidth limitation by preferentially storing frequently written sectors in cache memory during a databurst May 4, 2014 Issued
Array ( [id] => 11621957 [patent_doc_number] => 20170132144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'ENERGY-EFFICIENT DYNAMIC DRAM CACHE SIZING' [patent_app_type] => utility [patent_app_number] => 15/300272 [patent_app_country] => US [patent_app_date] => 2014-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15300272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/300272
Methods and systems for dynamic DRAM cache sizing Mar 28, 2014 Issued
Array ( [id] => 10894979 [patent_doc_number] => 08918609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'Storage apparatus and data management method to determine whether to migrate data from a first storage device to a second storage device based on an access frequency of a particular logical area' [patent_app_type] => utility [patent_app_number] => 14/199302 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 45 [patent_no_of_words] => 26882 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199302 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/199302
Storage apparatus and data management method to determine whether to migrate data from a first storage device to a second storage device based on an access frequency of a particular logical area Mar 5, 2014 Issued
Array ( [id] => 10879344 [patent_doc_number] => 08904142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Semiconductor memory system controlling writing of data to nonvolatile memories using consecutive logical addresses' [patent_app_type] => utility [patent_app_number] => 14/196187 [patent_app_country] => US [patent_app_date] => 2014-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 9851 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14196187 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/196187
Semiconductor memory system controlling writing of data to nonvolatile memories using consecutive logical addresses Mar 3, 2014 Issued
Array ( [id] => 9700564 [patent_doc_number] => 20140250249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'Concurrent Read And Write Memory Operations In A Serial Interface Memory' [patent_app_type] => utility [patent_app_number] => 14/171630 [patent_app_country] => US [patent_app_date] => 2014-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4890 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/171630
Interrupted write memory operation in a serial interface memory with a portion of a memory address Feb 2, 2014 Issued
Array ( [id] => 9465342 [patent_doc_number] => 20140129769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SYSTEM FOR DATA MIGRATION FROM A STORAGE TIER ALLOCATED TO A VIRTUAL LOGICAL VOLUME' [patent_app_type] => utility [patent_app_number] => 14/153406 [patent_app_country] => US [patent_app_date] => 2014-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 15937 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14153406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/153406
System for data migration using a migration policy involving access frequency and virtual logical volumes Jan 12, 2014 Issued
Array ( [id] => 10258062 [patent_doc_number] => 20150143059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'DYNAMIC WRITE PRIORITY BASED ON VIRTUAL WRITE QUEUE HIGH WATER MARK' [patent_app_type] => utility [patent_app_number] => 14/098563 [patent_app_country] => US [patent_app_date] => 2013-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5832 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14098563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/098563
DYNAMIC WRITE PRIORITY BASED ON VIRTUAL WRITE QUEUE HIGH WATER MARK Dec 5, 2013 Abandoned
Array ( [id] => 10034407 [patent_doc_number] => 09075726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Conflict resolution of cache store and fetch requests' [patent_app_type] => utility [patent_app_number] => 14/087200 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6442 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087200 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087200
Conflict resolution of cache store and fetch requests Nov 21, 2013 Issued
Array ( [id] => 9814452 [patent_doc_number] => 20150026397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'METHOD AND SYSTEM FOR PROVIDING MEMORY MODULE INTERCOMMUNICATION' [patent_app_type] => utility [patent_app_number] => 14/085937 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7572 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085937 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085937
METHOD AND SYSTEM FOR PROVIDING MEMORY MODULE INTERCOMMUNICATION Nov 20, 2013 Abandoned
Array ( [id] => 9513177 [patent_doc_number] => 20140149669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'CACHE MEMORY AND METHODS FOR MANAGING DATA OF AN APPLICATION PROCESSOR INCLUDING THE CACHE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/086188 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 16057 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086188
CACHE MEMORY AND METHODS FOR MANAGING DATA OF AN APPLICATION PROCESSOR INCLUDING THE CACHE MEMORY Nov 20, 2013 Abandoned
Array ( [id] => 12146680 [patent_doc_number] => 09880933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Distributed in-memory buffer cache system using buffer cache nodes' [patent_app_type] => utility [patent_app_number] => 14/085668 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 27083 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085668
Distributed in-memory buffer cache system using buffer cache nodes Nov 19, 2013 Issued
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