Search

Herve-louis Y. Assouman

Examiner (ID: 8745, Phone: (571)272-2606 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826, 2812
Total Applications
797
Issued Applications
665
Pending Applications
89
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20283840 [patent_doc_number] => 20250309082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Through Package Vertical Interconnect and Method of Making Same [patent_app_type] => utility [patent_app_number] => 19/238914 [patent_app_country] => US [patent_app_date] => 2025-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19238914 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/238914
Through package vertical interconnect and method of making same Jun 15, 2025 Issued
Array ( [id] => 20146770 [patent_doc_number] => 12381117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon [patent_app_type] => utility [patent_app_number] => 18/792267 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18792267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/792267
Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon Jul 31, 2024 Issued
Array ( [id] => 19546503 [patent_doc_number] => 20240363539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE HAVING CONTACT PLUG CONNECTED TO GATE STRUCTURE ON PMOS REGION [patent_app_type] => utility [patent_app_number] => 18/764355 [patent_app_country] => US [patent_app_date] => 2024-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764355
Semiconductor device having contact plug connected to gate structure on PMOS region Jul 3, 2024 Issued
Array ( [id] => 19532041 [patent_doc_number] => 20240355943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => ELECTRONIC IMAGING DETECTOR WITH THERMAL CONDUCTION LAYER [patent_app_type] => utility [patent_app_number] => 18/761587 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761587
ELECTRONIC IMAGING DETECTOR WITH THERMAL CONDUCTION LAYER Jul 1, 2024 Pending
Array ( [id] => 19515860 [patent_doc_number] => 20240347546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING SEGMENTED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/755041 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755041
Method of forming semiconductor device having segmented interconnect Jun 25, 2024 Issued
Array ( [id] => 20072325 [patent_doc_number] => 20250210547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING AN ELECTROMAGNETIC SHIELD AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/739950 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739950
SEMICONDUCTOR PACKAGE INCLUDING AN ELECTROMAGNETIC SHIELD AND METHOD OF FABRICATING THE SAME Jun 10, 2024 Pending
Array ( [id] => 19619485 [patent_doc_number] => 20240405165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => NEAR INFRARED PHOSPHOR AND LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/662576 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662576 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662576
NEAR INFRARED PHOSPHOR AND LIGHT EMITTING DEVICE May 12, 2024 Pending
Array ( [id] => 19420941 [patent_doc_number] => 20240297065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => CURVED SEMICONDUCTOR DIE SYSTEMS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/661094 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661094
Curved semiconductor die systems and related methods May 9, 2024 Issued
Array ( [id] => 19420670 [patent_doc_number] => 20240296794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => ORGANIC LIGHT-EMITTING DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/658590 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658590
Organic light-emitting display apparatus May 7, 2024 Issued
Array ( [id] => 19421111 [patent_doc_number] => 20240297235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => AIR SPACERS AROUND CONTACT PLUGS AND METHOD FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/658521 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658521 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658521
Air spacers around contact plugs and method forming same May 7, 2024 Issued
Array ( [id] => 19420975 [patent_doc_number] => 20240297099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SELF-ALIGNED CONTACT OPENINGS FOR BACKSIDE THROUGH SUBSTRATE VIAS [patent_app_type] => utility [patent_app_number] => 18/648132 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648132 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648132
SELF-ALIGNED CONTACT OPENINGS FOR BACKSIDE THROUGH SUBSTRATE VIAS Apr 25, 2024 Pending
Array ( [id] => 19484323 [patent_doc_number] => 20240332365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => LOW RESISTIVITY POLYCRYSTALLINE BASED SUBSTRATE OR WAFER [patent_app_type] => utility [patent_app_number] => 18/614485 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614485 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614485
LOW RESISTIVITY POLYCRYSTALLINE BASED SUBSTRATE OR WAFER Mar 21, 2024 Pending
Array ( [id] => 20237408 [patent_doc_number] => 20250294727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/605974 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605974
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Mar 14, 2024 Pending
Array ( [id] => 19486726 [patent_doc_number] => 20240334768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/597964 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597964
DISPLAY DEVICE Mar 6, 2024 Pending
Array ( [id] => 19837627 [patent_doc_number] => 20250089413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/597959 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597959
DISPLAY APPARATUS Mar 6, 2024 Pending
Array ( [id] => 20222976 [patent_doc_number] => 20250285907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => METHOD AND APPARATUS FOR PROCESSING SEMICONDUCTOR WAFER [patent_app_type] => utility [patent_app_number] => 18/597965 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597965 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597965
METHOD AND APPARATUS FOR PROCESSING SEMICONDUCTOR WAFER Mar 6, 2024 Pending
Array ( [id] => 20223016 [patent_doc_number] => 20250285947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => SEMICONDUCTOR PACKAGE WITH COMBINED LEAD FRAME AND CLIP FRAME [patent_app_type] => utility [patent_app_number] => 18/597324 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597324 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597324
SEMICONDUCTOR PACKAGE WITH COMBINED LEAD FRAME AND CLIP FRAME Mar 5, 2024 Pending
Array ( [id] => 19468195 [patent_doc_number] => 20240321865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/590804 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590804
SEMICONDUCTOR DEVICE Feb 27, 2024 Pending
Array ( [id] => 20932947 [patent_doc_number] => 12727151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-01 [patent_title] => Semiconductor structure including polysilicon as bottom layer of bit line structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/443656 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 8837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443656
SEMICONDUCTOR STRUCTURE INCLUDING POLYSILICON AS BOTTOM LAYER OF BIT LINE STRUCTURE AND METHOD OF MANUFACTURING THE SAME Feb 15, 2024 Pending
Array ( [id] => 20183994 [patent_doc_number] => 20250267952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => ELECTROSTATIC DISCHARGE PROTECTION FOR STACK DIE TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/443830 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443830 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443830
ELECTROSTATIC DISCHARGE PROTECTION FOR STACK DIE TECHNOLOGY Feb 15, 2024 Pending
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