| Application number | Title of the application | Filing Date | Status |
|---|
| 08/340133 | PLASMA DAMAGE REDUCTION DEVICE FOR SUB-HALF MICRON TECHNOLOGY | Nov 14, 1994 | Abandoned |
Array
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[patent_doc_number] => 05532506
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[patent_kind] => NA
[patent_issue_date] => 1996-07-02
[patent_title] => 'Integrated circuit adapted for improved thermal impedance'
[patent_app_type] => 1
[patent_app_number] => 8/339429
[patent_app_country] => US
[patent_app_date] => 1994-11-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/339429 | Integrated circuit adapted for improved thermal impedance | Nov 13, 1994 | Issued |
| 08/337916 | SEMICONDUCTOR DEVICE HAVING AN IMPROVED BURIED ELECTRODE FORMED BY SELECTIVE CVD | Nov 9, 1994 | Abandoned |
| 08/338101 | PANE ANTENNA HAVING AT LEAST ONE WIRE-LIKE ANTENNA CONDUCTOR COMBINED WITH A SET OF HEATING WIRES | Nov 8, 1994 | Abandoned |
| 08/335489 | COMPACT BROADBAND MICROSTRIP ANTENNA | Nov 6, 1994 | Abandoned |
| 08/333174 | MULTIPLE TRANSISTOR INTEGRATED CIRCUIT WITH THICK COPPER INTERCONNECT | Nov 1, 1994 | Abandoned |
Array
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[patent_app_type] => 1
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[patent_kind] => NA
[patent_issue_date] => 1995-10-03
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Array
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[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/330848 | Semiconductor device having resin gate hole through substrate for resin encapsulation | Oct 23, 1994 | Issued |
Array
(
[id] => 3602816
[patent_doc_number] => 05559362
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[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Semiconductor device having double metal connection layers connected to each other and to the substrate in the scribe line area'
[patent_app_type] => 1
[patent_app_number] => 8/323836
[patent_app_country] => US
[patent_app_date] => 1994-10-17
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[firstpage_image] =>[orig_patent_app_number] => 323836
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Array
(
[id] => 3626655
[patent_doc_number] => 05594269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-14
[patent_title] => 'Resistive load for integrated circuit devices'
[patent_app_type] => 1
[patent_app_number] => 8/322387
[patent_app_country] => US
[patent_app_date] => 1994-10-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/322387 | Resistive load for integrated circuit devices | Oct 11, 1994 | Issued |
Array
(
[id] => 3654379
[patent_doc_number] => 05606198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Semiconductor chip with electrodes on side surface'
[patent_app_type] => 1
[patent_app_number] => 8/321924
[patent_app_country] => US
[patent_app_date] => 1994-10-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/321924 | Semiconductor chip with electrodes on side surface | Oct 11, 1994 | Issued |
| 08/320777 | SEMICONDUCTOR MEMORY DEVICE HAVING CAPACITOR OF THIN FILM TRANSISTOR STRUCTURE | Oct 10, 1994 | Abandoned |
Array
(
[id] => 3594363
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[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Reliable low thermal resistance package for high power flip clip ICs'
[patent_app_type] => 1
[patent_app_number] => 8/319764
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319764 | Reliable low thermal resistance package for high power flip clip ICs | Oct 6, 1994 | Issued |
Array
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[patent_issue_date] => 1996-09-24
[patent_title] => 'Electronic label and carriers therefor'
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Array
(
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[patent_issue_date] => 1996-04-23
[patent_title] => 'Polishstop planarization structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319388 | Polishstop planarization structure | Oct 5, 1994 | Issued |
Array
(
[id] => 3583667
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[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Semiconductor device having peripheral metal wiring'
[patent_app_type] => 1
[patent_app_number] => 8/319140
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[firstpage_image] =>[orig_patent_app_number] => 319140
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319140 | Semiconductor device having peripheral metal wiring | Oct 5, 1994 | Issued |
| 08/316815 | METHOD FOR REDUCING REFLECTIVITY OF A METAL LAYER | Oct 2, 1994 | Abandoned |