Search

Hien N. Nguyen

Examiner (ID: 502, Phone: (571)272-1879 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2818, 2511
Total Applications
1992
Issued Applications
1913
Pending Applications
57
Abandoned Applications
40

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19964636 [patent_doc_number] => 12334151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Non-volatile memory stored with encoded data [patent_app_type] => utility [patent_app_number] => 18/771817 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 4008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771817
Non-volatile memory stored with encoded data Jul 11, 2024 Issued
Array ( [id] => 20266834 [patent_doc_number] => 12437830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 18/764906 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764906
Memory system Jul 4, 2024 Issued
Array ( [id] => 19943425 [patent_doc_number] => 12315561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Semiconductor memory devices with different word lines [patent_app_type] => utility [patent_app_number] => 18/763067 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763067 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763067
Semiconductor memory devices with different word lines Jul 2, 2024 Issued
Array ( [id] => 19533938 [patent_doc_number] => 20240357840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => THRESHOLD VOLTAGE-MODULATED MEMORY DEVICE USING VARIABLE-CAPACITANCE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/757685 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757685
Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same Jun 27, 2024 Issued
Array ( [id] => 19500138 [patent_doc_number] => 20240339156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => METHOD FOR PROGRAMMING MEMORY [patent_app_type] => utility [patent_app_number] => 18/748196 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748196 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748196
Method for programming memory Jun 19, 2024 Issued
Array ( [id] => 19661771 [patent_doc_number] => 20240428836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/746057 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746057
MEMORY SYSTEM Jun 17, 2024 Pending
Array ( [id] => 20132079 [patent_doc_number] => 12374396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Memory including metal rails with balanced loading [patent_app_type] => utility [patent_app_number] => 18/741201 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741201
Memory including metal rails with balanced loading Jun 11, 2024 Issued
Array ( [id] => 20148479 [patent_doc_number] => 12382841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Magnetic device and magnetic random access memory [patent_app_type] => utility [patent_app_number] => 18/677654 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 1286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677654
Magnetic device and magnetic random access memory May 28, 2024 Issued
Array ( [id] => 20352503 [patent_doc_number] => 20250349355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => ONE-WIRE SERIAL INTERFACE FOR LOW-BIT-COUNT PROGRAMMABLE RESISTIVE MEMORY [patent_app_type] => utility [patent_app_number] => 18/657741 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657741 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657741
ONE-WIRE SERIAL INTERFACE FOR LOW-BIT-COUNT PROGRAMMABLE RESISTIVE MEMORY May 6, 2024 Pending
Array ( [id] => 20080560 [patent_doc_number] => 12354635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => MRAM reference current [patent_app_type] => utility [patent_app_number] => 18/635929 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635929 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635929
MRAM reference current Apr 14, 2024 Issued
Array ( [id] => 20297634 [patent_doc_number] => 20250322877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/633244 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633244
MEMORY DEVICE AND OPERATING METHOD THEREOF Apr 10, 2024 Pending
Array ( [id] => 19858057 [patent_doc_number] => 12260907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Shared decoder architecture for three-dimensional memory arrays [patent_app_type] => utility [patent_app_number] => 18/622033 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 20049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622033 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622033
Shared decoder architecture for three-dimensional memory arrays Mar 28, 2024 Issued
Array ( [id] => 19740947 [patent_doc_number] => 12217786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Memory device, memory system having the same and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/613361 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 12079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613361 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613361
Memory device, memory system having the same and operating method thereof Mar 21, 2024 Issued
Array ( [id] => 19467683 [patent_doc_number] => 20240321353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Non-Volatile Memory Circuit with Self-Terminating Read Current [patent_app_type] => utility [patent_app_number] => 18/611468 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611468
Non-Volatile Memory Circuit with Self-Terminating Read Current Mar 19, 2024 Pending
Array ( [id] => 19494076 [patent_doc_number] => 12112797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-08 [patent_title] => Cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory macro and method for edge intelligence [patent_app_type] => utility [patent_app_number] => 18/602078 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602078
Cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory macro and method for edge intelligence Mar 11, 2024 Issued
Array ( [id] => 20196558 [patent_doc_number] => 20250273268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => READ-OUT CIRCUITS FOR RRAM-BASED CROSSBAR CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/587561 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587561 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587561
Read-out circuits for RRAM-based crossbar circuits Feb 25, 2024 Issued
Array ( [id] => 19237059 [patent_doc_number] => 20240194254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => METHODS OF CONTROLLING PCRAM DEVICES IN SINGLE-LEVEL-CELL (SLC) AND MULTI-LEVEL-CELL (MLC) MODES AND A CONTROLLER FOR PERFORMING THE SAME METHODS [patent_app_type] => utility [patent_app_number] => 18/583945 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583945
Methods of controlling PCRAM devices in single-level-cell (SLC) and multi-level-cell (MLC) modes and a controller for performing the same methods Feb 21, 2024 Issued
Array ( [id] => 19220346 [patent_doc_number] => 20240185050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => ANALOG NEUROMORPHIC CIRCUIT IMPLEMENTED USING RESISTIVE MEMORIES [patent_app_type] => utility [patent_app_number] => 18/442496 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442496
Analog neuromorphic circuit implemented using resistive memories Feb 14, 2024 Issued
Array ( [id] => 19912361 [patent_doc_number] => 12288579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Methods for independent memory bank maintenance and memory devices and systems employing the same [patent_app_type] => utility [patent_app_number] => 18/435696 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435696 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435696
Methods for independent memory bank maintenance and memory devices and systems employing the same Feb 6, 2024 Issued
Array ( [id] => 20389087 [patent_doc_number] => 12488820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Spin-orbit torque magnetoresistive random access memory and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/431533 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431533 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431533
Spin-orbit torque magnetoresistive random access memory and method of operating the same Feb 1, 2024 Issued
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