
Hien N. Nguyen
Examiner (ID: 502, Phone: (571)272-1879 , Office: P/2825 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2825, 2824, 2818, 2511 |
| Total Applications | 1992 |
| Issued Applications | 1913 |
| Pending Applications | 57 |
| Abandoned Applications | 40 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18205212
[patent_doc_number] => 11587614
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-21
[patent_title] => Read spike mitigation in integrated circuit memory
[patent_app_type] => utility
[patent_app_number] => 17/394778
[patent_app_country] => US
[patent_app_date] => 2021-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4672
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394778
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/394778 | Read spike mitigation in integrated circuit memory | Aug 4, 2021 | Issued |
Array
(
[id] => 17231975
[patent_doc_number] => 20210358532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => MRAM REFERENCE CURRENT
[patent_app_type] => utility
[patent_app_number] => 17/391639
[patent_app_country] => US
[patent_app_date] => 2021-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10836
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391639
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/391639 | MRAM reference current | Aug 1, 2021 | Issued |
Array
(
[id] => 18743078
[patent_doc_number] => 20230352066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-02
[patent_title] => RECONFIGURABLE MEMORY MODULE DESIGNED TO IMPLEMENT COMPUTING OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/040246
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 335
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18040246
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/040246 | Reconfigurable memory module designed to implement computing operations | Jul 29, 2021 | Issued |
Array
(
[id] => 17203233
[patent_doc_number] => 20210343328
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-04
[patent_title] => SEMICONDUCTOR MEMORY DEVICE HAVING CLOCK GENERATION SCHEME BASED ON COMMAND
[patent_app_type] => utility
[patent_app_number] => 17/376915
[patent_app_country] => US
[patent_app_date] => 2021-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8836
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376915
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/376915 | Semiconductor memory device having clock generation scheme based on command | Jul 14, 2021 | Issued |
Array
(
[id] => 17764550
[patent_doc_number] => 20220238163
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/372028
[patent_app_country] => US
[patent_app_date] => 2021-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7014
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372028
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/372028 | Memory device and method of operating the memory device | Jul 8, 2021 | Issued |
Array
(
[id] => 17346841
[patent_doc_number] => 20220013172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => CROSSBAR ARRAY APPARATUS AND WRITE METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/367641
[patent_app_country] => US
[patent_app_date] => 2021-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367641
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/367641 | Crossbar array apparatus and write method thereof | Jul 5, 2021 | Issued |
Array
(
[id] => 17708281
[patent_doc_number] => 20220208289
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/363735
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363735
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/363735 | Memory device and method of operating the same | Jun 29, 2021 | Issued |
Array
(
[id] => 18112652
[patent_doc_number] => 20230005532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => SYSTEMS AND METHODS FOR ADAPTIVE SELF-REFERENCED READS OF MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/364029
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10823
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364029
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364029 | Systems and methods for adaptive self-referenced reads of memory devices | Jun 29, 2021 | Issued |
Array
(
[id] => 18112653
[patent_doc_number] => 20230005533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => SYSTEMS AND METHODS FOR ADAPTIVE SELF-REFERENCED READS OF MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/364067
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10852
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364067
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364067 | Systems and methods for adaptive self-referenced reads of memory devices | Jun 29, 2021 | Issued |
Array
(
[id] => 18047098
[patent_doc_number] => 11521054
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-06
[patent_title] => Analog neuromorphic circuit implemented using resistive memories
[patent_app_type] => utility
[patent_app_number] => 17/362272
[patent_app_country] => US
[patent_app_date] => 2021-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 8190
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362272
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/362272 | Analog neuromorphic circuit implemented using resistive memories | Jun 28, 2021 | Issued |
Array
(
[id] => 18097058
[patent_doc_number] => 20220415399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => STATE DEPENDENT VPVD VOLTAGES FOR MORE UNIFORM THRESHOLD VOLTAGE DISTRIBUTIONS IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/359989
[patent_app_country] => US
[patent_app_date] => 2021-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13258
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359989
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/359989 | State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device | Jun 27, 2021 | Issued |
Array
(
[id] => 18097057
[patent_doc_number] => 20220415398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => BLOCK CONFIGURATION FOR MEMORY DEVICE WITH SEPARATE SUB-BLOCKS
[patent_app_type] => utility
[patent_app_number] => 17/360677
[patent_app_country] => US
[patent_app_date] => 2021-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17277
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360677
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/360677 | Block configuration for memory device with separate sub-blocks | Jun 27, 2021 | Issued |
Array
(
[id] => 18097076
[patent_doc_number] => 20220415417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => MEMORY PROGRAMMING WITH SELECTIVELY SKIPPED VERIFY PULSES FOR PERFORMANCE IMPROVEMENT
[patent_app_type] => utility
[patent_app_number] => 17/358516
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14612
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358516
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/358516 | Memory programming with selectively skipped verify pulses for performance improvement | Jun 24, 2021 | Issued |
Array
(
[id] => 17099958
[patent_doc_number] => 20210287749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-16
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/337936
[patent_app_country] => US
[patent_app_date] => 2021-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17878
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337936
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/337936 | Semiconductor memory device and method for operating thereof | Jun 2, 2021 | Issued |
Array
(
[id] => 18304240
[patent_doc_number] => 11626152
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-11
[patent_title] => Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling
[patent_app_type] => utility
[patent_app_number] => 17/324621
[patent_app_country] => US
[patent_app_date] => 2021-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 7654
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324621
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/324621 | Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling | May 18, 2021 | Issued |
Array
(
[id] => 19703998
[patent_doc_number] => 12198036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Spike timing dependent plasticity write method and synapse array apparatus
[patent_app_type] => utility
[patent_app_number] => 17/324062
[patent_app_country] => US
[patent_app_date] => 2021-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4557
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324062
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/324062 | Spike timing dependent plasticity write method and synapse array apparatus | May 17, 2021 | Issued |
Array
(
[id] => 17085247
[patent_doc_number] => 20210280254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-09
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/318337
[patent_app_country] => US
[patent_app_date] => 2021-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17893
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318337
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/318337 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THEREOF | May 11, 2021 | Abandoned |
Array
(
[id] => 18967205
[patent_doc_number] => 11900983
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-13
[patent_title] => Methods for independent memory bank maintenance and memory devices and systems employing the same
[patent_app_type] => utility
[patent_app_number] => 17/315654
[patent_app_country] => US
[patent_app_date] => 2021-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 7452
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315654
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/315654 | Methods for independent memory bank maintenance and memory devices and systems employing the same | May 9, 2021 | Issued |
Array
(
[id] => 17040395
[patent_doc_number] => 20210257031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => READ VOLTAGE CALIBRATION BASED ON HOST IO OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/313249
[patent_app_country] => US
[patent_app_date] => 2021-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16618
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313249
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/313249 | Read voltage calibration based on host IO operations | May 5, 2021 | Issued |
Array
(
[id] => 17908408
[patent_doc_number] => 11462268
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-10-04
[patent_title] => Generating hash codes for locality sensitive hashing
[patent_app_type] => utility
[patent_app_number] => 17/245115
[patent_app_country] => US
[patent_app_date] => 2021-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5563
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245115
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/245115 | Generating hash codes for locality sensitive hashing | Apr 29, 2021 | Issued |