Search

Hien N. Nguyen

Examiner (ID: 502, Phone: (571)272-1879 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2825, 2824, 2818, 2511
Total Applications
1992
Issued Applications
1913
Pending Applications
57
Abandoned Applications
40

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19803733 [patent_doc_number] => 20250069658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => Threshold Voltage Reduction in Memristive Devices [patent_app_type] => utility [patent_app_number] => 18/237787 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237787 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237787
Threshold Voltage Reduction in Memristive Devices Aug 23, 2023 Pending
Array ( [id] => 18820810 [patent_doc_number] => 20230395151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => INTERLEAVED STRING DRIVERS, STRING DRIVER WITH NARROW ACTIVE REGION, AND GATED LDD STRING DRIVER [patent_app_type] => utility [patent_app_number] => 18/237070 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237070
Interleaved string drivers, string driver with narrow active region, and gated LDD string driver Aug 22, 2023 Issued
Array ( [id] => 19626884 [patent_doc_number] => 12165731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/447910 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 21842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447910 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447910
Memory device Aug 9, 2023 Issued
Array ( [id] => 19604450 [patent_doc_number] => 20240395330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ENABLING SIGNIFICANT SCALING OF WORDLINE SWITCH WITH WORDLINE DEPENDENT NEGATIVE BITLINE VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/230078 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230078
Enabling significant scaling of wordline switch with wordline dependent negative bitline voltage Aug 2, 2023 Issued
Array ( [id] => 19459944 [patent_doc_number] => 12100445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Integrated circuit and method [patent_app_type] => utility [patent_app_number] => 18/362393 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362393
Integrated circuit and method Jul 30, 2023 Issued
Array ( [id] => 19749200 [patent_doc_number] => 20250037765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SUPPRESSING RANDOM TELEGRAPH NOISE IN CROSSBAR CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/361282 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361282
Suppressing random telegraph noise in crossbar circuits Jul 27, 2023 Issued
Array ( [id] => 20111289 [patent_doc_number] => 12362024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Memory device performing program operation and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/360593 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360593
Memory device performing program operation and method of operating the same Jul 26, 2023 Issued
Array ( [id] => 18776450 [patent_doc_number] => 20230371288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => THRESHOLD VOLTAGE-MODULATED MEMORY DEVICE USING VARIABLE-CAPACITANCE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/358867 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358867
Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same Jul 24, 2023 Issued
Array ( [id] => 19269063 [patent_doc_number] => 20240212767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MULTI-STAGE PROGRAMMING TECHNIQUES WITH THREE STATES PER MEMORY CELL PARITY [patent_app_type] => utility [patent_app_number] => 18/225248 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225248
Multi-stage programming techniques with three states per memory cell parity Jul 23, 2023 Issued
Array ( [id] => 18774007 [patent_doc_number] => 20230368837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING [patent_app_type] => utility [patent_app_number] => 18/357785 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357785
Memory including metal rails with balanced loading Jul 23, 2023 Issued
Array ( [id] => 18788024 [patent_doc_number] => 20230376417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY MAPPING FOR HIBERNATION [patent_app_type] => utility [patent_app_number] => 18/355161 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355161
Memory mapping for hibernation Jul 18, 2023 Issued
Array ( [id] => 18757229 [patent_doc_number] => 20230360687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => METHODS FOR ADJUSTING ROW HAMMER REFRESH RATES AND RELATED MEMORY DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/353776 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353776
Methods for adjusting row hammer refresh rates and related memory devices and systems Jul 16, 2023 Issued
Array ( [id] => 18757243 [patent_doc_number] => 20230360701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => PROGRAMMABLE RESISTIVE MEMORY ELEMENT AND A METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/353454 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353454
Programmable resistive memory element and a method of making the same Jul 16, 2023 Issued
Array ( [id] => 20080606 [patent_doc_number] => 12354681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Channel pre-charge process in a memory device [patent_app_type] => utility [patent_app_number] => 18/221649 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 8557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221649 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221649
Channel pre-charge process in a memory device Jul 12, 2023 Issued
Array ( [id] => 18926787 [patent_doc_number] => 20240029791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => MEMORY DEVICE WITH WRITE PULSE TRIMMING [patent_app_type] => utility [patent_app_number] => 18/352127 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352127
Memory device with write pulse trimming Jul 12, 2023 Issued
Array ( [id] => 18833545 [patent_doc_number] => 20230402072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => Storage System and Method for Circuit-Bounded-Array-Based Time and Temperature Tag Management and Inference of Read Thresholds [patent_app_type] => utility [patent_app_number] => 18/220363 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220363
Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds Jul 10, 2023 Issued
Array ( [id] => 18729096 [patent_doc_number] => 20230343391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => DUO-LEVEL WORD LINE DRIVER [patent_app_type] => utility [patent_app_number] => 18/345071 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345071
Duo-level word line driver Jun 29, 2023 Issued
Array ( [id] => 19064653 [patent_doc_number] => 11943930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor memory device and methods of manufacturing and operating the same [patent_app_type] => utility [patent_app_number] => 18/334583 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6332 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334583
Semiconductor memory device and methods of manufacturing and operating the same Jun 13, 2023 Issued
Array ( [id] => 19646275 [patent_doc_number] => 20240420795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ONE-TIME-PROGRAMMABLE (OTP) MEMORY WITH ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 18/334614 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334614 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334614
One-time-programmable (OTP) memory with error detection Jun 13, 2023 Issued
Array ( [id] => 18679516 [patent_doc_number] => 20230317172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/205679 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205679
Memory devices having source lines directly coupled to body regions and methods Jun 4, 2023 Issued
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