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Hiep Nguyen

Examiner (ID: 14657)

Most Active Art Unit
2816
Art Unit(s)
2816
Total Applications
656
Issued Applications
573
Pending Applications
5
Abandoned Applications
78

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6539230 [patent_doc_number] => 20100271078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'CIRCUITRY IN A DRIVER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/429491 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271078.pdf [firstpage_image] =>[orig_patent_app_number] => 12429491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/429491
Circuitry in a driver circuit Apr 23, 2009 Issued
Array ( [id] => 5567808 [patent_doc_number] => 20090251186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/414977 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7520 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20090251186.pdf [firstpage_image] =>[orig_patent_app_number] => 12414977 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/414977
Semiconductor integrated circuit Mar 30, 2009 Issued
Array ( [id] => 5389592 [patent_doc_number] => 20090206904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/367957 [patent_app_country] => US [patent_app_date] => 2009-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13778 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206904.pdf [firstpage_image] =>[orig_patent_app_number] => 12367957 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/367957
Semiconductor integrated circuit Feb 8, 2009 Issued
Array ( [id] => 191527 [patent_doc_number] => 07642841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Voltage supply insensitive bias circuits' [patent_app_type] => utility [patent_app_number] => 12/264235 [patent_app_country] => US [patent_app_date] => 2008-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3407 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642841.pdf [firstpage_image] =>[orig_patent_app_number] => 12264235 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/264235
Voltage supply insensitive bias circuits Nov 2, 2008 Issued
Array ( [id] => 5432811 [patent_doc_number] => 20090167397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Delay device for adjusting phase SMIA standard' [patent_app_type] => utility [patent_app_number] => 12/232935 [patent_app_country] => US [patent_app_date] => 2008-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2680 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20090167397.pdf [firstpage_image] =>[orig_patent_app_number] => 12232935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/232935
Delay device for adjusting phase SMIA standard Sep 25, 2008 Abandoned
Array ( [id] => 73110 [patent_doc_number] => 07755407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Variable delay circuit, testing apparatus, and electronic device' [patent_app_type] => utility [patent_app_number] => 12/233616 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8372 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/755/07755407.pdf [firstpage_image] =>[orig_patent_app_number] => 12233616 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233616
Variable delay circuit, testing apparatus, and electronic device Sep 18, 2008 Issued
Array ( [id] => 197924 [patent_doc_number] => 07639069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Tunable balanced loss compensation in an electronic filter' [patent_app_type] => utility [patent_app_number] => 12/151699 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3316 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639069.pdf [firstpage_image] =>[orig_patent_app_number] => 12151699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/151699
Tunable balanced loss compensation in an electronic filter May 7, 2008 Issued
Array ( [id] => 203719 [patent_doc_number] => 07633329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Single signal-to-differential signal converter and converting method' [patent_app_type] => utility [patent_app_number] => 12/107690 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5464 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633329.pdf [firstpage_image] =>[orig_patent_app_number] => 12107690 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107690
Single signal-to-differential signal converter and converting method Apr 21, 2008 Issued
Array ( [id] => 4857123 [patent_doc_number] => 20080265973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Semiconductor Device Having Transmitter/Receiver Circuit Between Circuit Blocks' [patent_app_type] => utility [patent_app_number] => 12/105586 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5382 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265973.pdf [firstpage_image] =>[orig_patent_app_number] => 12105586 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105586
Semiconductor device having transmitter/receiver circuit between circuit blocks Apr 17, 2008 Issued
Array ( [id] => 14940 [patent_doc_number] => 07808304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'Current switch for high voltage process' [patent_app_type] => utility [patent_app_number] => 12/099742 [patent_app_country] => US [patent_app_date] => 2008-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4379 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808304.pdf [firstpage_image] =>[orig_patent_app_number] => 12099742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099742
Current switch for high voltage process Apr 7, 2008 Issued
Array ( [id] => 4953042 [patent_doc_number] => 20080186066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Phase locked loop and phase locking method' [patent_app_type] => utility [patent_app_number] => 12/080012 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186066.pdf [firstpage_image] =>[orig_patent_app_number] => 12080012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/080012
Phase locked loop and phase locking method Mar 30, 2008 Issued
Array ( [id] => 4857111 [patent_doc_number] => 20080265961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/056896 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14383 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265961.pdf [firstpage_image] =>[orig_patent_app_number] => 12056896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/056896
Clock signal generation circuit and semiconductor device Mar 26, 2008 Issued
Array ( [id] => 75694 [patent_doc_number] => 07750696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Phase-locked loop' [patent_app_type] => utility [patent_app_number] => 12/077929 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/750/07750696.pdf [firstpage_image] =>[orig_patent_app_number] => 12077929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/077929
Phase-locked loop Mar 19, 2008 Issued
Array ( [id] => 264324 [patent_doc_number] => 07570093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-04 [patent_title] => 'Delay-locked loop and a delay-locked loop detector' [patent_app_type] => utility [patent_app_number] => 12/076319 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2520 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570093.pdf [firstpage_image] =>[orig_patent_app_number] => 12076319 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076319
Delay-locked loop and a delay-locked loop detector Mar 16, 2008 Issued
Array ( [id] => 4696055 [patent_doc_number] => 20080218239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Interface circuit and signal output adjusting method' [patent_app_type] => utility [patent_app_number] => 12/073698 [patent_app_country] => US [patent_app_date] => 2008-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3745 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20080218239.pdf [firstpage_image] =>[orig_patent_app_number] => 12073698 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073698
Interface circuit and signal output adjusting method Mar 6, 2008 Issued
Array ( [id] => 271041 [patent_doc_number] => 07564278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Power-on reset circuit' [patent_app_type] => utility [patent_app_number] => 12/030497 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3256 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564278.pdf [firstpage_image] =>[orig_patent_app_number] => 12030497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030497
Power-on reset circuit Feb 12, 2008 Issued
Array ( [id] => 5353394 [patent_doc_number] => 20090184738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Drive circuit for reducing inductive kickback voltage' [patent_app_type] => utility [patent_app_number] => 12/017070 [patent_app_country] => US [patent_app_date] => 2008-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5373 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20090184738.pdf [firstpage_image] =>[orig_patent_app_number] => 12017070 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/017070
Drive circuit for reducing inductive kickback voltage Jan 20, 2008 Issued
Array ( [id] => 4902193 [patent_doc_number] => 20080111606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'SET/RESET LATCH WITH MINIMUM SINGLE EVENT UPSET' [patent_app_type] => utility [patent_app_number] => 11/972233 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3931 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111606.pdf [firstpage_image] =>[orig_patent_app_number] => 11972233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972233
Set/reset latch with minimum single event upset Jan 9, 2008 Issued
Array ( [id] => 5407854 [patent_doc_number] => 20090121752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'SOURCE FOLLOWER' [patent_app_type] => utility [patent_app_number] => 11/967263 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3403 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121752.pdf [firstpage_image] =>[orig_patent_app_number] => 11967263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967263
Source follower Dec 30, 2007 Issued
Array ( [id] => 5320492 [patent_doc_number] => 20090058482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Duty detection circuit' [patent_app_type] => utility [patent_app_number] => 12/005923 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4031 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20090058482.pdf [firstpage_image] =>[orig_patent_app_number] => 12005923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/005923
Duty detection circuit Dec 27, 2007 Issued
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