
Hiep T. Nguyen
Examiner (ID: 18287, Phone: (571)272-4197 , Office: P/2131 )
| Most Active Art Unit | 2187 |
| Art Unit(s) | 2187, 2131, 2759, 2751, 2137, 2188, 2312, 2138 |
| Total Applications | 2185 |
| Issued Applications | 1977 |
| Pending Applications | 88 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13347369
[patent_doc_number] => 20180225224
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[patent_issue_date] => 2018-08-09
[patent_title] => REDUCING BANDWIDTH CONSUMPTION WHEN PERFORMING FREE MEMORY LIST CACHE MAINTENANCE IN COMPRESSED MEMORY SCHEMES OF PROCESSOR-BASED SYSTEMS
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/426473 | Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems | Feb 6, 2017 | Issued |
Array
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[patent_issue_date] => 2019-03-05
[patent_title] => Processing device with sensitive data access mode
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Array
(
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[patent_title] => DPU ARCHITECTURE
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Array
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[patent_issue_date] => 2019-01-15
[patent_title] => Software stack and programming for DPU operations
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Array
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[patent_doc_number] => 10482049
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[patent_issue_date] => 2019-11-19
[patent_title] => Configuring NVMe devices for redundancy and scaling
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Array
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[patent_issue_date] => 2017-11-28
[patent_title] => Recalling files stored on a tape
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/400154 | Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data | Jan 5, 2017 | Issued |
Array
(
[id] => 11544064
[patent_doc_number] => 20170097889
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[patent_title] => 'CACHING FOR HETEROGENEOUS PROCESSORS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/380328 | CACHING FOR HETEROGENEOUS PROCESSORS | Dec 14, 2016 | Abandoned |
Array
(
[id] => 11544063
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/380289 | Caching for heterogeneous processors | Dec 14, 2016 | Issued |
Array
(
[id] => 11458819
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[patent_issue_date] => 2017-02-23
[patent_title] => 'TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/345556 | Techniques for providing data redundancy after reducing memory writes | Nov 7, 2016 | Issued |
Array
(
[id] => 11882689
[patent_doc_number] => 09753862
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[patent_kind] => B1
[patent_issue_date] => 2017-09-05
[patent_title] => 'Hybrid replacement policy in a multilevel cache memory hierarchy'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/333681 | Hybrid replacement policy in a multilevel cache memory hierarchy | Oct 24, 2016 | Issued |
Array
(
[id] => 11570430
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/294125 | MEMORY SYSTEM | Oct 13, 2016 | Abandoned |
Array
(
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Array
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Array
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Array
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