Search

Hiep T. Nguyen

Examiner (ID: 18287, Phone: (571)272-4197 , Office: P/2131 )

Most Active Art Unit
2187
Art Unit(s)
2187, 2131, 2759, 2751, 2137, 2188, 2312, 2138
Total Applications
2185
Issued Applications
1977
Pending Applications
88
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13347369 [patent_doc_number] => 20180225224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => REDUCING BANDWIDTH CONSUMPTION WHEN PERFORMING FREE MEMORY LIST CACHE MAINTENANCE IN COMPRESSED MEMORY SCHEMES OF PROCESSOR-BASED SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/426473 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426473
Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems Feb 6, 2017 Issued
Array ( [id] => 14009661 [patent_doc_number] => 10223290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Processing device with sensitive data access mode [patent_app_type] => utility [patent_app_number] => 15/425877 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 6164 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/425877
Processing device with sensitive data access mode Feb 5, 2017 Issued
Array ( [id] => 12691870 [patent_doc_number] => 20180122456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => DPU ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/426033 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426033 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426033
DPU architecture Feb 5, 2017 Issued
Array ( [id] => 13807083 [patent_doc_number] => 10180808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Software stack and programming for DPU operations [patent_app_type] => utility [patent_app_number] => 15/426015 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 7773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426015 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426015
Software stack and programming for DPU operations Feb 5, 2017 Issued
Array ( [id] => 15137161 [patent_doc_number] => 10482049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Configuring NVMe devices for redundancy and scaling [patent_app_type] => utility [patent_app_number] => 15/423747 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423747
Configuring NVMe devices for redundancy and scaling Feb 2, 2017 Issued
Array ( [id] => 12932635 [patent_doc_number] => 09830085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-28 [patent_title] => Recalling files stored on a tape [patent_app_type] => utility [patent_app_number] => 15/407277 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6825 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15407277 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/407277
Recalling files stored on a tape Jan 16, 2017 Issued
Array ( [id] => 12194482 [patent_doc_number] => 09898212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-20 [patent_title] => 'Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data' [patent_app_type] => utility [patent_app_number] => 15/400154 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400154 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400154
Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data Jan 5, 2017 Issued
Array ( [id] => 11544064 [patent_doc_number] => 20170097889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'CACHING FOR HETEROGENEOUS PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/380328 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3643 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15380328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/380328
CACHING FOR HETEROGENEOUS PROCESSORS Dec 14, 2016 Abandoned
Array ( [id] => 11544063 [patent_doc_number] => 20170097888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'CACHING FOR HETEROGENEOUS PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/380289 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3643 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15380289 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/380289
Caching for heterogeneous processors Dec 14, 2016 Issued
Array ( [id] => 11458819 [patent_doc_number] => 20170052725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES' [patent_app_type] => utility [patent_app_number] => 15/345556 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345556 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345556
Techniques for providing data redundancy after reducing memory writes Nov 7, 2016 Issued
Array ( [id] => 11882689 [patent_doc_number] => 09753862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-05 [patent_title] => 'Hybrid replacement policy in a multilevel cache memory hierarchy' [patent_app_type] => utility [patent_app_number] => 15/333681 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 17244 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333681
Hybrid replacement policy in a multilevel cache memory hierarchy Oct 24, 2016 Issued
Array ( [id] => 11570430 [patent_doc_number] => 20170109074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/294125 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11540 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294125
MEMORY SYSTEM Oct 13, 2016 Abandoned
Array ( [id] => 12647325 [patent_doc_number] => 20180107606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => EVICTION CONTROL FOR AN ADDRESS TRANSLATION CACHE [patent_app_type] => utility [patent_app_number] => 15/294031 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294031
Eviction control for an address translation cache Oct 13, 2016 Issued
Array ( [id] => 12187646 [patent_doc_number] => 20180046582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'MEMORY EMULATION MECHANISM' [patent_app_type] => utility [patent_app_number] => 15/294413 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294413
Memory emulation mechanism Oct 13, 2016 Issued
Array ( [id] => 13859891 [patent_doc_number] => 10191664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 15/294255 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 12529 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294255
Memory system Oct 13, 2016 Issued
Array ( [id] => 12646764 [patent_doc_number] => 20180107419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => PERFORMING UPDATES ON VARIABLE-LENGTH DATA SEQUENTIALLY STORED AND INDEXED TO FACILITATE REVERSE READING [patent_app_type] => utility [patent_app_number] => 15/294505 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294505 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294505
Performing updates on variable-length data sequentially stored and indexed to facilitate reverse reading Oct 13, 2016 Issued
Array ( [id] => 13752591 [patent_doc_number] => 10169242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Heterogeneous package in DIMM [patent_app_type] => utility [patent_app_number] => 15/294387 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 17797 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294387 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294387
Heterogeneous package in DIMM Oct 13, 2016 Issued
Array ( [id] => 13807059 [patent_doc_number] => 10180796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 15/294119 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 12882 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294119 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294119
Memory system Oct 13, 2016 Issued
Array ( [id] => 11570428 [patent_doc_number] => 20170109072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/293975 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10715 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293975 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293975
MEMORY SYSTEM Oct 13, 2016 Abandoned
Array ( [id] => 16371210 [patent_doc_number] => 10802971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Cache memory transaction shielding via prefetch suppression [patent_app_type] => utility [patent_app_number] => 15/292740 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292740 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/292740
Cache memory transaction shielding via prefetch suppression Oct 12, 2016 Issued
Menu