Search

Hiep T. Nguyen

Examiner (ID: 18287, Phone: (571)272-4197 , Office: P/2131 )

Most Active Art Unit
2187
Art Unit(s)
2187, 2131, 2759, 2751, 2137, 2188, 2312, 2138
Total Applications
2185
Issued Applications
1977
Pending Applications
88
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12101092 [patent_doc_number] => 09858187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Buffering request data for in-memory cache' [patent_app_type] => utility [patent_app_number] => 14/922686 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 12947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14922686 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/922686
Buffering request data for in-memory cache Oct 25, 2015 Issued
Array ( [id] => 12475446 [patent_doc_number] => 09990400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Builder program code for in-memory cache [patent_app_type] => utility [patent_app_number] => 14/922733 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 12560 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14922733 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/922733
Builder program code for in-memory cache Oct 25, 2015 Issued
Array ( [id] => 11591520 [patent_doc_number] => 20170115931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'FLUSHLESS TRANSACTIONAL LAYER' [patent_app_type] => utility [patent_app_number] => 14/921044 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921044 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921044
Flushless transactional layer Oct 22, 2015 Issued
Array ( [id] => 11924641 [patent_doc_number] => 09792224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Reducing latency by persisting data relationships in relation to corresponding data in persistent memory' [patent_app_type] => utility [patent_app_number] => 14/921809 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 13668 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921809 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921809
Reducing latency by persisting data relationships in relation to corresponding data in persistent memory Oct 22, 2015 Issued
Array ( [id] => 11591708 [patent_doc_number] => 20170116118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SYSTEM AND METHOD FOR A SHARED CACHE WITH ADAPTIVE PARTITIONING' [patent_app_type] => utility [patent_app_number] => 14/921468 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10551 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921468
System and method for a shared cache with adaptive partitioning Oct 22, 2015 Issued
Array ( [id] => 11830715 [patent_doc_number] => 09727457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Minimizing latency due to garbage collection in a distributed system' [patent_app_type] => utility [patent_app_number] => 14/921753 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921753 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921753
Minimizing latency due to garbage collection in a distributed system Oct 22, 2015 Issued
Array ( [id] => 11614543 [patent_doc_number] => 09652401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Tagged cache for data coherency in multi-domain debug operations' [patent_app_type] => utility [patent_app_number] => 14/921244 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921244
Tagged cache for data coherency in multi-domain debug operations Oct 22, 2015 Issued
Array ( [id] => 11593616 [patent_doc_number] => 20170118028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'AUTHORIZING I/O COMMANDS WITH I/O TOKENS' [patent_app_type] => utility [patent_app_number] => 14/921871 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921871 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921871
Authorizing I/O commands with I/O tokens Oct 22, 2015 Issued
Array ( [id] => 13525821 [patent_doc_number] => 20180314453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => METHOD AND MEMORY MERGING FUNCTION FOR MERGING MEMORY PAGES [patent_app_type] => utility [patent_app_number] => 15/769725 [patent_app_country] => US [patent_app_date] => 2015-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15769725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/769725
Method and memory merging function for merging memory pages Oct 18, 2015 Issued
Array ( [id] => 11882715 [patent_doc_number] => 09753889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Gather using index array and finite state machine' [patent_app_type] => utility [patent_app_number] => 14/881111 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 19801 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14881111 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/881111
Gather using index array and finite state machine Oct 11, 2015 Issued
Array ( [id] => 12570825 [patent_doc_number] => 10019191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => System and method for protecting contents of shared layer resources [patent_app_type] => utility [patent_app_number] => 14/866299 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 9889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866299 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/866299
System and method for protecting contents of shared layer resources Sep 24, 2015 Issued
Array ( [id] => 10658303 [patent_doc_number] => 20160004447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'CLUSTERED RAID ASSIMILATION MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/854850 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854850
Clustered RAID assimilation management Sep 14, 2015 Issued
Array ( [id] => 11042465 [patent_doc_number] => 20160239421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'MEMORY NEST EFFICIENCY WITH CACHE DEMAND GENERATION' [patent_app_type] => utility [patent_app_number] => 14/851002 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4302 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851002 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851002
Memory nest efficiency with cache demand generation Sep 10, 2015 Issued
Array ( [id] => 10478097 [patent_doc_number] => 20150363114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'OPTIMIZING MEMORY USAGE ACROSS MULTIPLE GARBAGE COLLECTED COMPUTER ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 14/834787 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834787
Optimizing memory usage across multiple garbage collected computer environments Aug 24, 2015 Issued
Array ( [id] => 11220593 [patent_doc_number] => 09448930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Memory heaps in a memory model for a unified computing system' [patent_app_type] => utility [patent_app_number] => 14/833850 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833850
Memory heaps in a memory model for a unified computing system Aug 23, 2015 Issued
Array ( [id] => 10702315 [patent_doc_number] => 20160048463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'ASSIGNMENT CONTROL METHOD, SYSTEM, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/823134 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5262 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14823134 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/823134
Assignment control method, system, and recording medium Aug 10, 2015 Issued
Array ( [id] => 11896879 [patent_doc_number] => 09766814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Method and apparatus for defect management in a non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 14/822793 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7600 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822793 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/822793
Method and apparatus for defect management in a non-volatile memory device Aug 9, 2015 Issued
Array ( [id] => 11292540 [patent_doc_number] => 20160342472 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-11-24 [patent_title] => 'TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES' [patent_app_type] => utility [patent_app_number] => 14/821020 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/821020
Techniques for providing data redundancy after reducing memory writes Aug 6, 2015 Issued
Array ( [id] => 11292540 [patent_doc_number] => 20160342472 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-11-24 [patent_title] => 'TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES' [patent_app_type] => utility [patent_app_number] => 14/821020 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/821020
Techniques for providing data redundancy after reducing memory writes Aug 6, 2015 Issued
Array ( [id] => 13055325 [patent_doc_number] => 10049055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Managing asymmetric memory system as a cache device [patent_app_type] => utility [patent_app_number] => 14/808380 [patent_app_country] => US [patent_app_date] => 2015-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 19645 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14808380 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/808380
Managing asymmetric memory system as a cache device Jul 23, 2015 Issued
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